Detailed course info.
How to set up accounts and tools for the labs.
More information about the project topics presented in lecture.
Handouts and other documentation you may find useful.

Course Calendar with Handouts
Subject to Change.

Week Date Instr Lecture Assignments
1 Thu Aug 29 JL Lecture 1: The Fab-Design Interface. Industry economics and organization. Manufacturing, from silica mine to packaged chip. Dennard scaling and Moore's Law. Chip design styles: structured custom, standard cells, logic synthesis, systems on a chip, programmable standard parts. Class project and schedule. Lecture slides.
2 Tue Sep 3 JB Lecture 2: Introduction to Chisel hardware description language. Background on hardware design history and comparison to Chisel. Quick Scala for Chiselers. Algebraic syntax, types and literals, combinational circuits, wires, ports, bundles, vecs, and registers. Simple two step RTL semantics with single clock domain. Lecture slides. Lab 1 out
Thu Sep 5 JL Lecture 3: Timing. The GALS methodology. Combinational and clocked logic timing tutorial. Timing characterization of a new process. Pipelining, C-Slow retiming, and CLOS networks. Circuit details of flip-flops and inverters. Lecture slides.
3 Tue Sep 10 JL Lecture 4: Power and Energy. Overview of power issues in different product categoies. Transistor physics and the power wall. Design techniques: parallelism, power-down modes, multiple Vdds, clock gating, data-dependent processing, thermal management. Lecture slides.
Thu Sep 12 JB Lecture 5: ParLab + Aspire + RISC-V + Rocket + Accelerators. Overview of ParLab and Aspire projects. ASPIRE solution of ensemble of parallel pattern-specific accelerators. Overview of RISC-V ISA. Introduction to Rocket single-issue in-order pipeline implementation of RISC-V. Overview of ROCC coprocessor interface. Lecture slides. Lab 2 out
Fri Sep 13 Lab 1 due
4 Tue Sep 17 JL Lecture 6: Accelerator Projects. Power and energy techniques available for the project. Pareto optimality. The accelerator interface. Three worked project examples, and pointers to six other project ideas. Lecture slides.
Thu Sep 19 JB Lecture 7: Chisel Part II. Conditional updates on wires, registers, and memories. Demystifying Chisel and placing Chisel in categories of hardware languages. ROMs and combinational, sequential, and single port memories. Abstraction through object orientation and functional programming. Modules construction and bulk wiring. Standard library of modules. Lecture slides.
5 Tue Sep 24 JL+JB Lecture 8: Design verification strategies and Chisel based testing. Lecture slides part 1 and part 2. Lab 2 due
Thu Sep 26 JB Lecture 9: Overview of hardware design patterns. Lecture slides
6 Mon Sep 30 JB Chisel Bootcamp @ Sutardja Dai Hall / 8:30a-5p -- info and registration
Tue Oct 1 JL Lecture 10: Memory and memory design patterns. Lecture slides Lab 3 out
Thu Oct 3 JB Lecture 11: Design patterns for processing units and communication links. Ready-valid interfaces. An overview of Lab 3. Lecture slides part 1, part 2, and part 3.
7 Tue Oct 8 All Oral Project Proposals Project
Proposals Due
Thu Oct 10 All Oral Project Proposals
8 Tue Oct 15 All Private project meetings with groups. Lab 3 Due
Wed Oct 16 Lab 4 out
Thu Oct 17 All Private project meetings with groups.
9 Tue Oct 22 All Private project meetings with groups.
Thu Oct 24 All Private project meetings with groups.
Fri Oct 25 Lab 4 Due
10 Tue Oct 29 All Public project progress presentations.
Thu Oct 31 All Public project progress presentations.
11 Tue Nov 5 All Private project meetings with groups.
Thu Nov 7 All Private project meetings with groups.
12 Tue Nov 12 All Private project meetings with groups.
Thu Nov 14 All Private project meetings with groups.
13 Tue Nov 19 All Public project progress presentations.
Thu Nov 21 All Private project meetings with groups.
14 Tue Nov 26 All Private project meetings with groups.
Thu Nov 28 All Thanksgiving
15 Tue Dec 3 All Private project meetings with groups.
Thu Dec 5 All Private project meetings with groups.
16 Fri Dec 13 All Final Presentations from 9-11AM and 2-4PM in 380 Soda.
17 Wed Dec 18 All Final Project Reports due at 11:59PM (NO EXTENSIONS) .