Handouts for CS250: VLSI Systems Design
Fall 2012
Labs
Lab 1: GCD: VLSI's Hello World
Lab 2: Building your First Image Processing ASIC - updated on 9/23/2012
Lab 3: Design Space Exploration: Convolution Filter - updated on 10/16/2012
Tutorials
These two documents (along with the slides from lectures 2 and 3) are the most
comprehensive reference for the Chisel language currently available.
Chisel Tutorial - updated on 9/24/2012
Chisel Manual - updated on 9/24/2012
Tutorial 1: Using Git to Manage Source RTL
Synopsys Application Notes
You may find these enlightening (only accessible from Berkeley IP addresses).
Coding Guidelines for Datapath Synthesis
DesignWare Datapath and Building Block IP Quick Reference
Synopsys 90nm Digital Design Workshop slides
These slides provide a thorough explanation of all facets of an ASIC physical design flow,
using Synopsys tools and targeting their 90nm educational library. They are in PowerPoint
format - make sure to read the presenter notes associated with each slide. Some of the
topics covered (e.g. design for testing, improving yield, etc) aren't relevant for CS250,
but most of them are.
Lecture 1: Intro: What are the new challenges to design 90nm SOCs?
Lecture 2: Design environment and tool chain
Lecture 3: Design synthesis
Lecture 4: Leakage aware design/prevention (esp. SRAMs)
Lecture 5: Design Planning/Floorplanning (FP) for Low Power
Lecture 6: Library analysis and management (standard cell, IO, memory)
Lecture 7: Low Power Flow, positioning the different techniques to minimize dynamic and leakage power, consequence on the flow
Lecture 8: Physical Synthesis: Placement and optimization
Lecture 9: Multiple Clock Tree Synthesis
Lecture 10: Physical Synthesis: Test
Lecture 11: Physical Synthesis: MultiMode and MultiCorner
Lecture 12: Physical Synthesis: Routing to GDS2
Lecture 13: IR drop analysis, requirement to do dynamic power analysis in 90nm
Lecture 14: Introduction to multimode multi-corner simulation. Introduction to OCV (On-chip variation) and SSTA (Statistical Static Timing Analysis)
Lecture 15: Sign-Off
Lecture 16: Design finishing & layout verification
Lecture 17: Tape-out
Tutorial: Power-Performance Optimization of Digital Circuits
These slides give a good overview of the area/energy tradeoffs in VLSI design. The first
set focuses on digital circuit optimization in general (energy-delay sensitivity,
circuit optimization, architecture optimization), and the second set deals specifically
with the Synopsys ASIC tool flow.
Part 1: Digital Circuit Optimization
Part 2: Low-Power Synthesis/Labs