1) Hitting your head on the desk doesn't help
after the first time.
2) Use all the resources around you, especially
the other students in lab.
3) Design Manager reports warnings because they
help you debug! There's even a hierarchy so
it's not totally impossible to track down
unloaded wires etc.
$Xblahblahblah refers to a component or wire on
page X of the main schematic.
$3XYZ\blah\blah refers to a subcomponent in
Highlighting any component will cause the name
of that component (in computer and human readable
form) to be displayed on the bottom right hand
corner of the screen.
4) Run old tests whenever you suspect something
got screwed up. Ptest is a good for testing UART.
Check2.bit test wiring/chips.
5) Output useful signals to unused pins so you
can trigger on a particular event/block. So
output start_block so you can zoom in and see
what a particular block is doing on the scope.
6) Bugs tend to creep into programs past 3am.
Be very careful if you choose to debug while
you're tired. Take breaks to refresh yourself
and don't stare at the screen for 6 hours in
7) Alot of times bugs are "obvious" mistakes.
Debug the components your partner designed
rather than your own. Or try explaining
what your block does to your partner.
Stupid mistakes make alot of sense until
you catch yourself saying them out loud.
Most importantly, nobody said it would be
easy, so don't expect it to be!
(From page 4-110 in Xilinx manual).
Here is a list of pins which are not available to use for
extra debugging outputs:
HDC P36 (high during configuration, then general IO)
LDC P37 (low during configuration, then general IO)
VCC P2, P11, P22, P33, P42, P54, P63, P74,
GND P12, P21, P31, P43, P52, P64, P76, P1
Don't put outputs on the switch lines because you will fry your Xilinx
if the switch is in the wrong position. These lines are inputs only!
P19, P20, P23, P24, P25, P26, P27, P28
I don't know if this still occurs with the current version of the software.