Lab 7 - Wire-Wrap and SRAMs

The purpose of this lab is to get an understanding of how RAM works.

Before you start your wiring, verify that your Xilinx board works. Download U:\WVLIB\CS150\LAB7.BIT to your board and make sure it cycles through the addresses once. On this .BIT file, switch 1 will enable/disable the clock to the design, so make sure it is set properly.
Set aside A LOT of time for this lab. Wiring the Xilinx board can take a few hours. Designing and implementing your FSM may take a few more hours. Debugging can take a lot longer. So, start at least two days before your scheduled lab time.
You will need to use the computers in 123 Cory for this lab. Most of the computers have XChecker cables, so you will be able to download designs to the Xilinx board.
Now that you know where to do the lab and how long it will take, what's the first thing you should do? Read the lab handout of course!
You will have to do most of the lab before you come to your lab section. For the prelab, you will have to show the TA:
- Your neatly wire-wrapped Xilinx board. Neat means that all the wires are flat on the board and you have used different colors for the address lines and the data lines. You must also have your wire wrap ID (from the checkoff sheet of the lab) on your Xilinx board.
- Your schematics for your FSM and the ViewSIM and/or ViewTrace output showing you have simulated your design.
I recommend you place your SRAM in one of the corners, because you will be getting a few more chips. This way you can have your chips spaced out and the wiring will be less confusing.
After you are done wiring your Xilinx board and SRAM, use the TA provied BIT file to test your wiring. It's at U:\WVLIB\CS150\LAB7.BIT. In ViewDraw, you can look at the interface schematic at LAB7.1 in the CS150 library to see which switches do what. If this bit file does not work on your board, the most probable cause is you have messed up your Wire Wrap wiring.
Your FSM should do exactly what the TA design does. It should first write the output of the LFSR to the SRAM, then read it back and check the output against the LFSR. If there is a difference in the values from the SRAM and the LFSR, your FSM should go to a stop state. If there is never an error, the FSM will continue this write then read cycle forever.
A way to introduce an error into the SRAM is to ground one of the address lines during the write cycle. This will cause the data from the LFSR to be written to the wrong address. During the read cycle, the TA design your design should detect an error and stop.
Here's what Brian has to say about Lab7:

Just a few reminders for lab 7. The TA bit file in U:wvlib/cs150 is updated. If you got in on friday, it would probably be best if you copied it into your directory again. This goes the same with the pinout file Lab7.1 as well. In the bit file, there are counters and shift registers already put there for you. There's an 8 bit counter hooked up to pin 13. Pin 13 is the internal quartz clock located on the Xilinx board. That's right! No more clock from the Xchecker cable. This puppy will run by itself. For your convenience, there are som eswitches you may use. Switch 1 (that's the dipswitch on the upper bank of switches, and all the way to the left) will turn the clock on and off. If the clock is off, the spare button will act as the clock. One spare button press per clcok cycle. Pretty neat huh?

Switch 2 (tht one next to it) will change the display to the numerical LED's. The address lines of the SRAM (which, incidentally, is the ouput to the 16 bit counter) are fed into these LED's. However, since the LED's can only ouput 8 bits, switch 2 will choose whether to show the 8 most significant bits, or the 8 least significant bits.
When switch 2 is off (OPEN), it will output the 8 MSB. Under normal operation, the least significant bits move too fast to see. It will display an 88. The middle decimal point is tied to the error signal. When that lights up, then your counters will stop, and you know that there's something wrong with the data at that counter address. The left most decimal point is pinned to OE.H. When it's lit, you know that you're reading from the SRAM.

Operation of the FSM is pretty easy. Upon reset, all the counters and the LFSR should be reset. The contents of teh LFSR should be written into the SRAM. Then increment the counter and LFSR. When all the addresses have been written to (when TC of the 16 bit counter is asserted), reset the counters and the LFSR. Compare this value with that in the LFSR. If it's the same, increment both the counter and LFSR and repeat until You've compared all of the contents of the SRAM (we give you a comparater). Return to the "write cycle" and start all over again. Under normal operations, this design should just run over and over again.

As a final word of precaution, read the TA schematic carefully so you know what control signal you must use, and what you must supply. Remember the 3 stage write sequence and look over the lab specs CAREFULLY before doing the lab.

Good Luck

-Brian Choi

Back to main page