It is assumed that you have read over the lab handout and are familiar
with the naming conventions of the wires and familiar with the
components used in this lab.

Okay, here's the run down of everything you need to know for
lab 5.  Lab 5 uses a Linear Feedback Shift Register to compute
parity bits for any message.  The message is of size (2^n)-1.
Of these, n bits are the parity bits.  This means the actual
size of transmittable data is (2^n)-n-1 bits.
How this LFRS works is weel out of the scope of this
course and will not be explained here.  Simply consider the
LFSR  as a black box.  You can shift in (2^n)-n-1 data bits
along with n parity bits, some "magic" happens, and you can tell
if there is an error in your data.  If there is an error (up to
1 bit), you can repair the damage.

The bitfields for the entire "message" bit stream look like:
["data" bits: (2^n)-n-1 bits]["parity" bits: n bits]

These are written in MSB order (most significant bit on the left)
This entire bit stream is shifted into the LFSR.  For the purpose
of this lab, you directly control the parity bits, via the dip
switches (SW5).  If you set all the parity bits to "0" and shift
the entire message stream through, the value of the LFSR will be the
"indentity" parity bits.  If you were to change the parity bits
(again using the dip switches) to the "identity" bits and shift
the entire message through, the value of the LFSR will be zero.
It is important to note that the value of the LFSR is the value of the
outputs of the Flip-Flops of the Shift Registers.  NOT the value of
any XOR gates that may be at the output of the Flip-Flops.  If you
mislabel the wires, you may end up wasting time by debugging a problem
that doesn't really exist.

These identity "parity" bits are only valid for a particular set of "data"
bits shifted in (so different bits will naturally result in different
identity bits).  In the event that the "data" stream was altered, but
the orginal "identity" parity bits were used, the LFSR would no longer show all
"0"s.  This makes it easy to tell if our data was corrupted.  However
it is not enough that we want to know if our data was transmitted intact,
we also want to be able to recover the corrupted bits.  As stated before,
if the data is corrupted, the the LFSR will return a non-zero after all the
bits are shifted in.  This number in the LFSR is called the "symptom".
If you were to run the the "data" stream (with the 1 bit error) into the LFSR
along with all "0's" for the parity bits, you would observe this same "symptom"
after shifting in "X" many bits.  This number X would correspond to the
location of the error.  This is the crucial part of the lab which makes Error
Correction algorithm tick.  It is important to understand this last paragraph.
The example of how this works is shown in the lab hand out.

The hardware representation of implementing this algorithm is fairly simple.
Our FSM requires two different modes.  MODE 1 is needed to find the identity
"parity" bits.  The dip switches should all be preset to zero. In mode 1,
the machine should shift in all the data and parity bits through the LFSR.
The data bits are found in the ROM schematic.  After all the bits are shifted
through, the value of the LFSR will show the identity "parity" bits".  If you
were to put these identity bits into the dip switches and ran MODE 1 again,
the LFSR would show all 0's (exactly what we explained in the previous
paragraphs).  If we were to introduce an error in the ROM, and ran MODE 1
again with the identity "parity" bits on the dip switches, we would see a
non-zero value on the LFSR.  Instead, we would see the "symptom" on the LFSR.
By plugging this "symptom" into the dip switches, we will need to run the
data stream through the LFSR until the output of the LFSR is the same as the
symptom.  This is done in MODE 0.  The number of shifts through the LFSR it
took to get this symptom is the same as the location of the error.

So for MODE 1, the LFSR must shift out all the bits of the ROM.  Your Control
FSM will know when this is finished when the TC of the Counteris asserted (=1).
In MODE 0, the LFSR must shift out all the bits of the ROM until the LFSR
matches the value on the dip switches.  The comparator will assert a signal
high when both of its inputs are equal.  The value of the counter (as shown on
the numerical LED's) shows the location of the error.  The FSM which you must
create will have a run state and a halt state.  The machine should enter the
run state when RESET is asserted.  Depending on the MODE, it will transition to
the halt state as prescribed by the conditions above.  Your FSM only needs to
enable the counter and the shift register (both of which must be reset when the
RESET control signal is asserted) when it is the run state.

-Brian Choi