Lab 3 - Finite State Machine on Xilinx
In this lab, you will be downloading the schematic you created in Lab 2 onto the Xilinx chip.
There shouldn't be too much thinking for this lab, just follow the directions and you should
end up with a lock with a code on the Xilinx chip. You will not be able to complete the
entire lab outside of 204B Cory. You will be able to convert the schematic to EDIF file format
and compile to the BIT file before lab.
- IT IS IMPORTANT THAT YOU ARE CAREFUL WITH THE XILINX BOARD! Plug them in
the right way, do not try to remove the wiring on the board, and do not remove the board from
the computer station.
- You need to have the correct settings in your WorkView project file. If you don't have the
following search order in your project, your project may not work:
- U:\WVLIB\CS150
- U:\WVLIB\XC4000E (xc4000e)
- U:\WVLIB\XBUILTIN (xbuiltin)
- U:\WVLIB\XC4000 (xc4000)
- You will have to add the TA provided schematic called LAB3.1 in the CS150 library. It contains
the components necessary to connect your design from lab 2 to the outside world, like the enter and
reset buttons, code switches, etc. Save LAB3.1 as the second page to your schematic (e.g., FSM.2).
- Follow the directions in the lab to convert your ViewDraw schematic to the EDIF file format
and then to the Xilinx BIT format for downloading to the Xilinx. If you get an error about WIR file
BUILTIN:PULLDOWN not being found, you probably have set up your WorkView project wrong. The way one
student fixed it is to create a new project in a new directory and copy the SCH and SYM directories
from the old project directory to the new project directory.
- It's a good idea to name all of your nets and components, otherwise, you will get cryptic
error or warning messages about nets and components with names like $N1/$N3 when compiling
from the EDIF file to the BIT file.
- Always look at the reports generated after the compilation to check for warnings or errors. The
TA provided schematic has warnings about CLK and RIP, so you can ignore those.
- One of the Xilinx boards is an older version that has different DIP switches. It's ON and OFF
are the reverse of ON and OFF on the other board.
- If you get an error about INIT not being high when downloading a design, make sure that SW4 (the lower
bank of DIP switches) has everything open except for SW4-7 (the seventh switch).
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