Checkpoint 2 - Video Interface
Note: What I had here about the FSM for checkpoint 2 before Monday
afternoon was wrong. For this checkpoint, you will just need to show the signals from the sync separator,
A/D, and the VCLK to the A/D on the oscilloscope.
- For your TA Meeting, you will need to have completed state diagrams for your
project. You will need to show your TA exactly how your project will work. For
example, you will need to show how your project will save each pixel to the SRAM
in Mode 1, or how the data will be sent to the computer via the serial transmitter.
- For your prelab, you must have all of the video interface wired up. You will
not need to change any of the wiring from Lab7 and Checkpoint 1, so ignore anything
in the Checkpoint 2 handout that says to change OE on the SRAM to Pin 18. Your
Lab7 and Checkpoint 1 designs should still work after completing the video
interface wiring!
- To test your wiring, you can download U:\WVLIB\CS150\CHECK2.BIT to your
Xilinx board. From U:\WVLIB\CS150\CAMERAFALL98, copy CAMERA.EXE and CAMERA.CFG
to your own directory. Edit the PORT line in the CAMERA.CFG file (put COM2 if
in 204B Cory, COM4 if in 123 Cory). After downloading the design and connecting
the serial cable to your Xilinx board, run CAMERA.EXE from your directory.
- The CHECK2.BIT design will start in Mode 1 (Frame Dump) and then immediately
go to Mode 2 after sending one frame (this is different behavior then how
your project should work). From then on, hitting the SPARE button will toggle
between modes after sending the data for one frame.
- When you have the Camera program running, it should start displaying
a picture or a graph of vectors depending on what mode you are in. The debug
dialog box should show how many frames have been sent and how many bytes.
- On the oscilloscope, you will have to show
the analog video signal, COMP SYNC, VSYNC, VCLK to the A/D, A/D OE, and the
8 bits of data from the A/D. It will be sufficent to create the clock divider for VCLK
and tie the OE for the A/D to high.
- A/D timing explained by Kevin:
The best timing to get a digital data would be on the falling edge 3 cycles
after. Actually, the digital data is already available before the falling
edge - typically 18ns after the third rising edge after the sampling falling
edge. Since your FSM would be working with the rising or falling clock edge,
it's impossible for you to get a data 18ns after the third rising. Therfore,
the first available edge is the falling edge 3 cycles after. In addition,
you can still read the data on the next rising edge as in the figure 3. But
keep in mind that in 18ns, the data will be gone and the next sampled data
will be availabe on the output pins.
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