University of California at Berkeley
College of Engineering
Department of Electrical Engineering and Computer Sciences
CS 150, Fall 1998 J. Wawrzynek, N. Weaver
September 11, 1998 Modified by R. Fearing, D. Young, and N. Aboobaker

Lab 3

Finite State Machine on Xilinx

1 Objective

Put your combination lock from Lab 2 onto a chip. To do this, you will:

  1. Use Xilinx Design Manager to compile and route your design.
  2. Use Xilinx Hardware Debugger to do real-time hardware debugging and watch internal signals
1.1 Overview
Figure 1.  Steps taken in this lab to compile, download, and test design

For a design to be useful, it must make its way into hardware. To do this we will be using Xilinx Field Programmable Gate Arrays (FPGAs), chips that can be configured as many different circuits. Specifically, we will be using the Xilinx XC4000 Design Demonstration Board, which contains an XC4005E FPGA, switches, and light-emitting diodes.

These boards are very expensive and not easily replaced. Be very careful with these. Make sure that they stay on the anti-static mat. Make sure also that the ground plug is plugged in. Before touching the Xilinx board, ground yourself-- touch any metal you can find or the static mat.

Do not take the Xilinx boards or anything else from 204B Cory!

2 Prelab

  1. Answer the questions on the checkoff sheet.
  2. Make sure your Lab 2 design works and the labels in your schematic match the labels shown in the example.
  3. Also check that none of your filenames are long than 8 characters. We're using new software so this might or might not be a problem (it's better to be safe though).
  4. Make sure your schematic does not use any components from the builtin library. If you followed the instructions in Lab 2, this should not be a problem.
  5. Make sure none of your symbols or components have the same name as components in the (xc4005e) library, such as DFF or CLB. If you did, rename your components.
2.1 Xilinx Interface

To compile your design for the Xilinx, some interface components need to be added. We have done the busy work for you. (See section 3.1 below)

2.1.1 I/O Pads

I/O pads and buffers are special cells in the (xc4005e) library, connect the Xilinx to the outside world of buttons, LEDs, and other chips:

IPAD Input Pad OPAD Output Pad
IBUF Input Buffer OBUF Output Buffer
Each IPAD and OPAD is connected to a particular pin on the Xilinx, designated by the LOC attribute. For example, in our schematic, the IPAD in the upper-left corner, SW5-1, has the attribute LOC=P27, indicating it connects to pin 27 of the Xilinx.

2.1.2 Debounce

Your lock expects ENTER and RESET to be high for exactly one clock cycle every time it is pressed. The DEBOUNCE circuit, a simple state machine, ensures this.

3 Add the Xilinx Interface Circuits

We have entered the required interface circuits; you need to copy them into your design. You need to open the TA-provided design and save it as the second sheet in your combination lock schematic.

Like on one-sheet schematics, nets with the same label on different sheets of the same schematic are connected implicitly.

  1. Start ViewDraw. Open the lab3.1 in the (cs150) library.
  2. Choose File -> Save Copy As. Enter FSM.2 [Note: If you named the top level of your lab 2 combination lock something other than FSM, you'll need to substitute your filename for FSM]
  3. Open FSM.2 in Viewdraw. Do File -> Save and Check. Examine the design demonstration board schematic in your reader and note how the XC4005[A] is connected to the LEDs, DIP switches, etc.
4 Export your design to an EDIF file

In order to compile your schematic, you first need to export your schematic into an EDIF file. Note that the EDIF file is created from the wire file that is updated when you do Save and Check from inside ViewDraw.  So, it's very important to use Save and Check to save your design.

  1. Click on the EDIF icon on the WorkView toolbar.
  2. Click on the EDIF Net List Writer tab near the top of the window that appears.
  3. Set Input to the name of the wire file for the schematic you're working on (in our example, projdir\wir\FSM.1). The output field should be filled in automatically.
  4. In the Level field near the middle of the window, select Xilinx M1 from the list. If you don't do this, you will get an error about the WIR file BUILTIN:PULLDOWN not being found.
  5. Click on the Apply button at the bottom of the window. Note any errors and hit Cancel to close the window.
These steps will create a file with the .EDN extension.

5 Run Xilinx Design Manager to Compile Your Schematic

Xilinx Design Manager will compile and route the EDIF netlist into a bit file that can be downloaded to the Xilinx chip. Xilinx Design Manager maintains a project file like Workview Office's Project Manager. However, the two are different and unrelated. The first thing you'll need to do is set up a Xilinx Design Manager project file.

5.1 Making a Xilinx Design Manager project file

  1. Start Xilinx Design Manager. It is a program in the Xilinx directory. There should be a shortcut to it on the desktop called Dsgnmgr. If you get an error about opening a project, just click on OK, and ignore the error.
  2. Choose File->New Project from the menu bar.
  3. Enter the name of the EDIF file you created (or click the Browse button and find the file). This file will be located in the directory that was created when you did Lab 2.
  4. Save the project file by choosing File->Save.
5.2 Compile Your Design

Once you have created a project file, you can generate the .BIT file. .BIT files are different depending on the chip that you're compiling for, so the correct settings have to be entered. This semester we're using the XC4005E-PC84-4

  1. Choose Design->Implement from the menu bar in Xilinx Design Manager.
  2. Set the following parameters by clicking the Select button:
  3. Family XC4000E
    Device 4005E
    Package PC 84
    Speed grade -4
  4. Click the Run button. A new window will pop up showing the progress of the compilation and routing. During this process a bunch of output files with very detailed information are created. If there are errors, view the log file. Even if the compilation is successful, you can read the log file to find out some details of the compilation and routing.
  5. There is a tool that let you see graphically the resulting mapping of the logic in the Xilinx chip. Select Tools->EPIC Design Editor. You should take a look, since it's pretty neat to see.
6 Download and Test the Circuit

Xilinx's Hardware Debugger is a real-time hardware debugging tool. With it, you can step through clock cycles and observe the actual values of internal nodes! (This is new. We didn't have this capability in previous semesters.) If you check the TA provided schematics, you'll notice that it includes a "readback" block. This is used to recover the values of internal nodes. It is a component in the CS150 directory.

6.1 Connect the power cables and XChecker cables

The power supplies have a cable with two banana plugs, red and black, and a yellow lead. The black is ground, the red is +5V, and the yellow is -5V. Don't attach the -5V connector to anything, and make sure it doesn't touch anything metal!

  1. Plug in the power supply.
  2. Ground yourself.
  3. Connect the black banana plug to the board.
  4. Connect the red banana plug. The decimal point on CR3 (the left seven-segment LED) should light, indicating the power is on.
You'll also need to plug in the XChecker cable. It has a rectangular plug connected to a bunch of wires. It only fits in one direction. You shouldn't have to force it. (One of the openings in the plug is filled with epoxy. It corresponds to the area without a pin on the board.) Ask your TA if you have any questions here.

6.2 Download the circuit

  1. Start Hardware Debugger by choosing Tool->Hardware Debugger from the Xilinx Design Manager menu bar. If this complains about the cable not being connected correctly, make sure the board has power and the XChecker cable is attached.
  2. You can also check the cable configuration by choosing Cable->Communcations.  The XChecker cable is hooked up to COM1 and the transfer rate should be 115 Kbps.
  3. Choose File->New->Project and enter the name of the newly created .BIT file. (For example, FSM.BIT)
  4. Choose Download->Download Design or double-click on the name of the bit file in the diagram to download the design to the Xilinx board. In this lab, a zero should appear on the CR4 (the right 7-seg LED), indicating that the machine is in State 0.
6.3 Observe the circuit in operation

The clock signal for the combination lock design comes from the XChecker cable and is fed into pin 8 of the Xilinx chip (see schematic). This is useful for debugging because the software allows us to manually control the clock. To manipulate the clock, we'll use the Hardware Debugger "Readback Control Panel". From the control panel, we can also watch the internal signals and have the waveforms displayed like in ViewTrace.

6.3.1 Turn on the clock

Since the clock is coming from the XChecker cable, the lock will not operate properly until the clock is running.

  1. Open the Readback Control Panel by choosing View->Control Panel from Hardware Debugger.
  2. On the far right, click the circle next to Start in the Clock Control section of the control panel. You can also apply single clock pulses by clicking the apply button while Stop is selected.
6.3.2 Test the circuit

While the clock is running, test out your circuit changing the combination and pressing the enter button.

  1. Test a successful combination using the buttons and switches on the design demonstration board.
  2. Test an unsuccessful combination.
  3. Make sure SW 4-7 (marked RST on the board) is closed. Otherwise, the RESET button won't work.

    Have your TA check off your working lock when done with the rest of the lab.

6.3.3 View the internal variables

Open the Readback Control Panel.

  1. Click on the Groups button. Combine state2, state1, and state0 into a group called "state".  You'll need to click the New button to make a new group, and the Save button for the changes to take effect.
  2. Click on the Displays button to display waveforms for state, error, open, and enter.  To select "state" for display, select "Groups" from the Display section (at the top of the Display Signals dialog box). To select error, open, and enter for display, "Signals" must be selected. After clicking OK, a waveform window will pop up.
  3. Go through both a successful and unsuccessful attempt at opening the lock, taking a snapshot (click the Read button) after each state transition (for this lab, you can leave the clock running while you do this).
  4. To read the value of the groups, you can click with the left mouse button on the part of the waveform you want to see.  Also, pressing the plus symbol will expand the group waveform into separate single waveforms.
  5. Show your TA the generated waveform for checkoff.

Lab 3 Checkoff Sheet