This lab is meant to expose you to the most concrete level of FPGA development. Throughout the rest of the semester you will be focusing on more abstract methods of describing circuits, and the tools that are used to transform that description into actual hardware. As you will see, being able to represent hardware in a more abstract way increases productivity and design flexibility, but also hides some of the details of the FPGA platform. Completing this lab will help to establish the underlying architecture of the FPGA in your mind, as well as help you make optimal design decisions in the future.
Please make sure you do the prelab before attending your lab section, you may find the lab to be long and frustrating otherwise.
You fill find the answers to these in the prelab. 1. How many SLICEs are in a single CLB? 2. How many inputs do each of the LUTs on a Virtex-5 LX110T FPGA have? 3. How many of LUTs does the LX110T have? 4. How do you implement logic functions of 7 inputs in a single SLICEL? How about 8? 5. What is the difference between a SLICEL and a SLICEM?
In this lab, you will use a tool called FPGA Editor to manipulate logic and nets in a simple design. Throughout the lab, you will verify that your work in FPGA Editor is correct by programming your FPGA with your design file and seeing it come to life in hardware. For simple verification purposes, circuits you build in this lab will take their input from switches on the board and use LEDs as outputs. For example, the design file provided for you by the staff as a starting point implements the logical or of two DIP switches and shows the result on an LED.
# tar -xf ~cs150/public_html/sp11/lab_1/lab1.tar.gz
# cd lab1
The archive is also available here: lab1.tar.gz
To get started, open a terminal. This can be accomplished by hitting alt-f2
and typing gnome-terminal, followed by return. To start up FPGA Editor with
the DefaultDesign:
# fpga_editor DefaultDesign.ncd DefaultDesign.pcf
The main project view shown below presents several windows that you will use throughout the lab. The Array Window(titled Array1) shows you a schematic of the FPGA you are working with. It highlights the parts of the FPGA that are currently utilized, as well as the connections between these components.
The List Window(titled List1) allows you to find and sort components and nets by name. The World Window(titled World1) shows a mini-map of the entire FPGA, outlining the portion currently being shown in the Array Window. The Console Output at the bottom of the screen prints messages that often contain useful diagnostic information. The Toolbar near the top of the screen contains a handful of useful buttons. Mousing over each button reveals its name. Some of the most frequently used are:
Finally, the Buttonbar on the far right of the screen contains buttons that let you modify the design.
Now that you are familiar with the main FPGA Editor view, you can begin to look
at the design described by DefaultDesign.ncd. As mentioned before, this design
is very simple and implements the circuit depicted below. In this design,
GPIO_LED[0-7]
are the connections coming from the LEDs along the bottom of the
XUPv5, while GPIO_DIP[0-7]
represents the connections coming from the DIP
switches along the bottom right of the board.
You will now explore the design with FPGA Editor, locating the LUT which implements the logical OR function.
File->Main Properties...
, set the Edit Mode
field to Read Write
, click Apply
and click Close
.Type
field set
to SLICEL
and write down the contents of it's Site
field on your checkoff
sheet.f11
and left click on the red slice that appears in the Array
Window.editblock
button in the Buttonbar.You should now see a window(titled Block1), shown below, displaying the
internals of the SLICEL
you selected in the List Window. It is important to
note the background color of this window. If the background is black, the slice
may be modified, if it is gray, the slice is read only. To toggle the editing
mode, click the Begin Editing
button in the top left corner of the window.
On the left side of the SLICEL
you will see four LUTs, each with two outputs.
The Default Design only uses one output from one of the LUTs. Write down the
name of the LUT's output net on your checkoff sheet. You now have fairly good
visibility of your design. You know exactly which SLICEL
implements this
simple design, and you also know which LUT in that SLICEL
implements the
logic function, now you will verify that the logic function it implements, is
the one you expect.
Now that you know the exact details of what the Default Design implements, you will now test the design in practice.
To run BitGen exectue the following:
# bitgen DefaultDesign.ncd DefaultDesign.bit DefaultDesign.pcf
This simple command takes the DefaultDesign.{ncd,pcf} files and translates them into a .bit file. Once it is done running you should be able to locate the DefaultDesign.bit file that was produced.
The last step is to invoke Impact to program the FPGA, unfortunately the command line interface to Impact is a little clunky, and since you will ever only use Impact to program the LX110T chip on the XUPv5, the staff provides a simple wrapper script that contains all of the functionality you should need this semester. Simply execute the following:
# ezimpact DefaultDesign.bit
Once the message '5': Programmed successfully.
is displayed, the FPGA has been
configured with your .bit file.
Locate the DIP switches in the lower right corner, and the LEDs in the lower center of the XUPv5, your board should now be showing the results of a logical OR between switch 1 and switch 2 on LED 0. Change the positions of the two switches and note the change in LED 0.
Find and write down the following: 1. Site number of SLICE used to implement OR. 2. Name of net connected to output port of the LUT implementing OR. 3. LUT attributes used to implement OR.
Now that you know how to view the FPGA implementation of your circuits at the lowest level, you will begin to make modifications to show off the power of the LUT. Specifically, you are going to add a DIP switch to your design, connect it to the LUT computing OR and change the logic function computed by that LUT to match the design below.
Notice that you can easily increase the complexity of the logic function being implemented, without needing to use more LUTs.
Edit Mode
to Read Write
.SLICEL
.f11
.So far what you have done is familiar from the previous design. This time, however, you are going to first connect the third DIP switch to the slice. Shown below is the slice that implements the OR function, as well as the nets connected to the slice, and that slice's input and output pins.
Circled are six of the input pins(triangles pointing to the right) to the slice,
these are the six inputs to the LUT implementing the or function. Notice that
blue lines extend from two of these input pins, these blue lines are the nets
representing DIP switches 1 and 2, and have the names GPIO_DIP[0]
and
GPIO_DIP[1]
. You will now connect GPIO_DIP[2]
, the third DIP switch.
Unrouted Nets
from the drop-down
box.GPIO_DIP_c[2]
.site.pin = SLICE_X17Y100.C5, comp.pin =
N_XX_i.CXX
).ctrl
and click the unrouted net
labeled GPIO_DIP_c[2]
in the List Window.route
in the
Buttonbar on the right.ERROR:FPGAEditor:361 - Nothing found to
route.
autoroute
button located on the Buttonbar.At this point you should see the input port you selected connected with a line
to GPIO_DIP[2]
like the other two inputs to your LUT. Now that the DIP switch
is connected, you will alter the logic performed by the LUT.
editblock
in the Buttonbar.and: *
or: +
not: ~
xor: @
File->Save
, and follow the previous instructions
for BitGen and Impact to test your Augmented Design.Once you have successfully programmed your FPGA and verified correct behaviour, take a moment to contemplate the power of the LUT. As you have seen you were able to add a relatively significant amount of logic to your or gate without using any more FPGA logic resources. In short, the LUT is not limited by the complexity of the logic it implements, but by the number of input and output ports it has.
The last part of the lab will utilize everything you have learned in the
previous sections. You will be modifying the Lightshow(diagram below), which is
a simple circuit that lights up multiple LEDs in a sequence and has already been
completed for you. Your task is to fix the Enable
signal.
The current design implements an Enable
signal that is high only when DIP
switches 1 and 2 are high. As can be seen above, the design calls for an
Enable
signal that is high when all DIP switches 1 through 8 are
high(GPIO_DIP[0-7]). You are going to implement this design in two ways:
F7{A,B}MUX
and F8MUX
and a single level of LUTs(no routing signals
between LUTs through the FPGA fabric).Follow these suggestions to avoid some FPGA Editor pitfalls:
F7{A,B}MUX
and F8MUX
, realize that FPGA Editor
will not autoroute
signals connected to those muxes if the inputs to the
LUTs connected to those muxes are already routed. Connect the selects of the
muxes before you do anything else!Reminder: Save all your .bit files for checkoff!