CS150 - Agenda

Week	Date	Lecture & Readings	Homework	Lab & Project
1	Tue 1/18	Lec #1: Course Introduction Slides		Course Lab Guide
1	Thu 1/20	Lec #2: Synchronous Digital Systems Review (1) Slides Reading: DDCA: 1.1-1.3, review 1.4, 1.5-1.6, review 6.1-6.3		Course Lab Guide
2	Tue 1/25	Lec #3: FPGA Architecture Introduction Slides Reading: Chapter 5 of the Virtex-5 User's Guide (PreLab reading)	HW1	Lab #1: FPGA Physical Layout (FPGA Editor)
2	Thu 1/27	Lec #4: Synchronous Digital Systems Review (2) Slides	HW1	Lab #1: FPGA Physical Layout (FPGA Editor)
3	Tue 2/1	Lec #5: Verilog Primer Slides Reading: DDCA: Chapter 4	HW2	Lab #2: Structure Verilog FPGA Flow
3	Thu 2/3	Lec #6: CAD Tools (Synthesis) Slides	HW2	Lab #2: Structure Verilog FPGA Flow
4	Tue 2/8	Lec #7: CAD Tools (Simulation) Slides	HW3	Lab #3: Verilog Synthesis FPGA Flow
4	Thu 2/10	Lec #8: CMOS Implementation Technologies Slides	HW3	Lab #3: Verilog Synthesis FPGA Flow
5	Tue 2/15	Lec #9: MIPS Processor Implementations Slides Reading: DDCA: 7.1-7.3, 7.6	HW4	Lab #4: Circuit Simulation and Testing
5	Thu 2/17	Lec #10: Project Introduction: Serial I/O Slides	HW4	Lab #4: Circuit Simulation and Testing
6	Tue 2/22	Lec #11: 3-stage processor pipeline structure, SRAM pt. 1 Slides	HW5	Lab #5: Serial
6	Thu 2/24	Lec #12: SRAM pt. 2, cache organization Slides Reading: Pages 111 through 137 of the Virtex-5 User's Guide And DDCA 8.1-8.3	HW5	Lab #5: Serial
7	Tue 3/1	Lec #13: DRAM technology and interfacing (J. Lazzaro) Slides	HW6	Checkpoint #1: Pipelined MIPS150
7	Thu 3/3	Lec #14: Video interface and framebuffers Slides	HW6	Checkpoint #1: Pipelined MIPS150
8	Tue 3/8	Lec #15: Line drawing engine, Ethernet interface Slides Midterm 1 is Wednesday 3/9, 6-9pm in 125 Cory	HW7
8	Thu 3/10	Lec #16: Timing (1) Slides	HW7
9	Tue 3/15	Lec #17: Timing (2)	HW8
9	Thu 3/17	Lec #18: Cache Design	HW8
10	Tue 3/22	Spring Break, No Lecture	No homework. Work on your project!
10	Thu 3/24	Spring Break, No Lecture	No homework. Work on your project!
11	Tue 3/29	Lec #19: Combinational Logic Slides Reading: DDCA: Chapter 2		Checkpoint #2: Ethernet Interface
11	Thu 3/31	Lec #20: Finite State Machines Slides Reading: DDCA 3.4		Checkpoint #2: Ethernet Interface
12	Tue 4/5	Lec #21: Design Blocks (1) Slides Reading: DDCA: 5.1-5.4	HW9	Checkpoint #3: DRAM & Caches
12	Thu 4/7	Lec #22: Design Blocks (2) Slides	HW9	Checkpoint #3: DRAM & Caches
13	Tue 4/12	Lec #23: Design Blocks (3) Slides	HW10
13	Thu 4/14	Lec #24: Design Blocks (4) Slides	HW10
14	Tue 4/19	Lec #25: System Organization (1) Midterm 2 is Wednesday 4/20, 6-9pm	HW11	Checkpoint #4: Frame Buffer & Graphics Engine
14	Thu 4/21	Lec #26: System Organization (2) Slides	HW11	Checkpoint #4: Frame Buffer & Graphics Engine
15	Tue 4/26	Lec #27: System Organization (3)	HW12
15	Thu 4/28	Lec #28: Course Wrap-up Slides	HW12
16	Tue 5/3	RRR Week, No Lecture		Cleanup & Optimizations, Early Checkoff
16	Thu 5/5	RRR Week, No Lecture		Cleanup & Optimizations, Early Checkoff
17	Mon 5/9	Final Exam is Monday 5/9, 11:30-2:30		Final Project Checkoff
18	Mon 5/16	Final Report due Monday 5/16, 8:00am		Final Report