| EECS150 Components and Design Techniques for Digital Systems | |
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EECS150 Spring 2009 Calendar |
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Home | Old News | Calendar | Grades | Grading Status | Project Status | Documents | Staff | Syllabus | Schedule | Old Websites | Links | TA |
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| Calendar [1/18/2009-5/16/2009] | ||||
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| Week | Date | Lecture | Homework | Lab |
| 1 | Tue 1/20 | Lec #1: Course Introduction & MIPS ISA Review: [PDF] |
Lab Lec #1: [PDF] [PPT] | |
| Thr 1/22 | Lec #2: Synchronous Digital Systems Review (1): [PDF] Reading: DDCA: 1.1-1.3, review 1.4, 1.5-1.6, review 6.1-6.3 |
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| 2 | Tue 1/27 | Lec #3: FPGA Architecture Introduction: [PDF] Reading: Chapter 5 of the Virtex-5 User's Guide (PreLab reading) |
HW #1: [PDF] (Due Fri, Jan 30 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Lab #1: FPGA Physical Layout (FPGA Editor): [ZIP] [PDF] Lab Lec #2: [PDF] [PPT] |
| Thr 1/29 | Lec #4: Synchronous Digital Systems Review (2): [PDF] |
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| 3 | Tue 2/3 | Lec #5: Verilog Primer: [PDF] Reading: DDCA: Chapter 4 |
HW #2: [PDF] (Due Fri, Feb 6 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Lab #2: Structure Verilog FPGA Flow: [ZIP] [PDF] Lab Lec #3: [PDF] [PPT] |
| Thr 2/5 | Lec #6: CAD Tools (Synthesis): [PDF] |
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| 4 | Tue 2/10 | Lec #7: CAD Tools (Simulation): [PDF] |
HW #3: [PDF] (Due Fri, Feb 13 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Lab #3: Verilog Synthesis FPGA Flow: [ZIP] [PDF] Lab Lec #4: [PDF] [PPT] |
| Thr 2/12 | Lec #8: CMOS Implementation Technologies: [PDF] |
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| 5 | Tue 2/17 | Lec #9: MIPS Processor Implementations: [PDF] Reading: DDCA: 7.1-7.3, 7.6 |
HW #4: [PDF] (Due Fri, Feb 20 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Lab #4: Circuit Simulation and Testing: [ZIP] [PDF] Lab Lec #5: [PDF] [PPT] |
| Thr 2/19 | Lec #10: Project Introduction: Serial I/O: [PDF] |
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| 6 | Tue 2/24 | Lec #11: Project Introduction: Pipelineing, Memory Basics: [PDF] |
HW #5: [PDF] (Due Fri, Feb 27 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Lab #5: ChipScope and the UART/CPU Adaptor: [ZIP] [PDF] Lab Lec #6: [PDF] [PPT] |
| Thr 2/26 | Lec #12: Project Introduction: Memory Blocks, Project Specification: [PDF] Reading: Pages 111 thru 137 of the Virtex-5 User's Guide |
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| 7 | Tue 3/3 | Lec #13: Project Introduction: Video Interface: [PDF] |
HW #6: [PDF] (Due Fri, Mar 6 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Checkpoint #1: Pipelined MIPS150: [PDF] Lab Lec #7: [PDF] [PPT] |
| Thr 3/5 | Lec #14: Project Introduction: Graphics, Bit-shifters: [PDF] |
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| 8 | Tue 3/10 | Lec #15: Energy and Power (John Lazzaro): [PDF] |
HW #7: [PDF] (Due Fri, Mar 13 @ 14:10) Solution: [PDF] Quiz |
Checkpoint #1: Pipelined MIPS150 (cont.) Lab Lec #8: [PDF] [PPT] |
| Thr 3/12 | Lec #16: Timing: [PDF] |
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| 9 | Tue 3/17 | Lec #17: Combinational Logic (1): [PDF] Reading: DDCA: Chapter 2 |
HW #8: [PDF] (Due Fri, Mar 20 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Checkpoint #1 DUE: [S] [HEX] Lab Lec #9 |
| Thr 3/19 | Lec #18: Combinational Logic (2): [PDF] |
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| 10 | Tue 3/24 | No Lecture | No Lab Lecture | |
| Tue 3/24 | Spring Break | |||
| Thr 3/26 | No Lecture | |||
| 11 | Tue 3/31 | Lec #19: Combinational Logic (3): [PDF] |
HW #9: [PDF] (Due Fri, Apr 3 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Checkpoint #2: Serial/Console Interface Lab Lec #10 |
| Wed 4/1 | Midterm I (Evening, 6-9p) Score Distribution |
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| Thr 4/2 | Lec #20: Finite State Machines: [PDF] |
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| 12 | Tue 4/7 | Lec #21: Design Blocks (1): [PDF] Reading: DDCA: 5.1-5.4 |
HW #10: [PDF] (Due Fri, Apr 10 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Checkpoint #2 DUE: [S] [HEX] Lab Lec #11: [PDF] [PPT] |
| Thr 4/9 | Lec #22: Design Blocks (2): [PDF] |
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| 13 | Tue 4/14 | Lec #23: Design Blocks (3): [PDF] |
HW #11: [PDF] (Due Fri, Apr 17 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Checkpoint #3: Frame Buffer: [ZIP] [PDF] Lab Lec #12: [PDF] [PPT] |
| Thr 4/16 | Lec #24: Design Blocks (4): [PDF] |
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| 14 | Tue 4/21 | Lec #25: System Organization (1): [PDF] |
HW #12: [PDF] (Due Fri, Apr 24 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Checkpoint #4: Line Drawing Engine & Checkpoint #3 DUE: [PDF] Lab Lec #13: [PDF] [PPT] |
| Thr 4/23 | Lec #26: System Organization (2): [PDF] |
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| 15 | Tue 4/28 | Lec #27: System Organization (3): [PDF] |
HW #13: [PDF] (Due Fri, May 1 @ 14:10) Solution: [PDF] Quiz: [PDF] |
Checkpoint #5: Optimizations & Checkpoint #4 DUE, Early Checkoff Lab Lec #14: [PDF] [PPT] |
| Thr 4/30 | Lec #28: Graphics Processors (John Lazzaro): [PDF] |
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| 16 | Tue 5/5 | Lec #29: Asynchronous Circuits (Adam Megacz): [PDF] |
HW #14: [PDF] (Due Fri, May 8 @ 14:10) Solution: [PDF] Quiz |
Checkpoint #5 DUE, Final Checkoff Lab Lec #15 |
| Thr 5/7 | Lec #30: Course Wrap-up: [PDF] |
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| 17 | Tue 5/12 | No Lecture | No Lab Lecture | |
| Thr 5/14 | No Lecture | |||
| Thr 5/14 | Final Exam: 12:30-3:30pm | |||
| Last Updated: 01/24/2009 by | |
| Chris Fletcher |