EECS 150 Components and Design Techniques for Digital Systems    
CS 150 Spring 2008

Tu/Th 2:00-3:30PM
289 Cory
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Old News


As some help for last-minute preparation, some old exam solutions have been uploaded to the course website. There are some good MT2/Final exam type questions on there.


Remember that the final exam is tomorrow (5/15) and will be held in 125 Cory.


There will be a second final exam review session tomorrow (5/14) at 3pm in light of the scheduling confusion with the midterm 2 review and previous final review session.


Along with the review session at 6pm tomorrow, we will be holding another midterm 2 review at 5pm to accommodate everyone who could not make it today.


There will be a review today of midterm 2 and its solutions held at 6pm in the 150 lab.


Discussion sections are cancelled for this final week. There will be a review session held on Tuesday from 5-8pm and Wednesday, depending on the need.


Two Sample Final Reports have been posted on the website. Both of which received very high grades.


The lab lecture for the project report will be held next Friday, April 25th. Good luck on the project!


Small updates/clarifications made to the Checkpoint 4 specifications. Please note that the DCT takes in an 8 bit UNSIGNED input, so you should put all 8 bits of your luma values in, instead of the 7 bits that was originally on the spec.


Lab Lecture for CP4 is up now. Sorry for the delay, but some modifications have been made to the protocol to remove ANNOUNCE packets. Instead we will leave the functionality that it introduced as extra credit. The Checkpoint 4 spec will be uploaded as soon as those changes have been made.


Updated Checkpoint 2.5 spec is now posted (Now with more pictures!). Please update your copy. Hope you all have loads of FUN working on it.


There will be no lab lecture this Friday. Enjoy your break or whatever you can salvage of it...


For checkpoint 1 checkoff, we expect to receive a bit file and your verilog source code. (We don't need your project files, only SDRAMControl.v and AddressCounter.v) Also, be sure to send in a team name. From now on, you will be identified by this name.


IMPORTANT CLARIFICATION FOR CP1: The DONE signal should be held high in the Idle state and the READY signal should be held high indefinitely after initialization has completed

Also, for submission of assignments, please email your code, project file and bitfile to cs150sp08@gmail.com by the start of your lab section.


The new and improved Checkpoint 2 specifications and files have been posted. Please ensure that you have this version of the spec and not the previous version


Checkpoint2 spec and zip files have temporarily been taken down due to needed updates. We will try to have them back up ASAP.


All documentation relevant to checkpoint2 has been uploaded. VEncoderChkptSp07.doc and VEncoderLabLectureSp07.ppt are uploaded as references in case anyone is interested in becoming more familiarized with the Video Encoder module and the ITU-R BT.601/656 standards.


A sample design document is posted (this is a design document for a checkpoint you will not do this semester). Note that this design document only received a 95/100 (Graded by Shah himself).


The solutions to midterm #1 have been posted


This is a reminder that Midterm 1 will be held tomorrow (Feb 26th) from 2-3:30 in 125 Cory. Please see the newsgroup for preparation material.


The review session for Midterm 1 will be held in 125 Cory from 8-10pm this Sunday.


Welcome to the Spring 2008 semester of CS150! Please check this web site often, as course updates and materials will be posted here. We look forward to a great semester!

-CS150 Staff

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UC Berkeley http://www-inst.eecs.berkeley.edu/~cs150/ EECS 150 Spring 2008