module l6p3 (clk, rst_in, ok) ;

input clk;
input rst_in;
output ok;

reg ok;

wire [7:0] agen;
wire [7:0] bgen;
wire [15:0] macgen;
wire [15:0] mac;
wire end_test;

wire rst;

assign rst = ~rst_in;

mac_mod m (clk, rst, agen, bgen, mac);

test_fsm t (clk, rst, agen, bgen, macgen, end_test);

parameter [1:0] //synopsys enum STATE_TYPE
    s0 = 2'b00,
    s1 = 2'b01,
    s2 = 2'b10;

reg [2:0] /* synopsys enum STATE_TYPE */ cs;
reg [2:0] /* synopsys enum STATE_TYPE */ ns;

//synopsys state_vector cs

    always @ (negedge clk or posedge rst) 
    begin
	if (rst) cs = s0;
	else cs = ns;
    end

    always @ (cs)
    begin 
    	case (cs) //synopsys full_case
            s0: begin
		ok = 1'b1;
		if ((macgen!=mac)) ns = s2;
		else if ((macgen==mac) && end_test) ns = s1;
		else ns = s0;
	    end 
            s1: begin
		ok = 1'b0;
		ns = s1;
	    end 
            s2: begin
		ok = 1'b1;
		ns = s2;
	    end 
    	endcase
    end 
    
endmodule


module mac_mod (clk, rst, a, b, mac) ;

input clk;
input rst;
input [7:0] a;
input [7:0] b;
output [15:0] mac;

reg [7:0] a_in;
reg [7:0] b_in;
reg [15:0] mac;

wire [15:0] mac_out;
wire [15:0] add1_in1;
wire [15:0] add1_in2;
wire [15:0] add1_out;
wire [15:0] add2_in1;
wire [15:0] add2_in2;
wire [15:0] add2_out;
wire [15:0] add3_in1;
wire [15:0] add3_in2;
wire [15:0] add3_out;
wire [15:0] add4_in1;
wire [15:0] add4_in2;
wire [15:0] add4_out;
wire [15:0] add5_in1;
wire [15:0] add5_in2;
wire [15:0] add5_out;
wire [15:0] add6_in1;
wire [15:0] add6_in2;
wire [15:0] add6_out;
wire [15:0] add7_in1;
wire [15:0] add7_in2;
wire [15:0] add7_out;
wire [15:0] add8_in1;
wire [15:0] add8_in2;
wire [15:0] add8_out;

reg [7:0] ashift0;
reg [7:0] ashift1;
reg [7:0] ashift2;
reg [7:0] ashift3;
reg [7:0] ashift4;
reg [7:0] ashift5;
reg [7:0] ashift6;
reg [7:0] ashift7;

always @ (a_in or b_in)
begin
if (b_in[0]) ashift0=a_in;
else ashift0=8'b0;
if (b_in[1]) ashift1=a_in;
else ashift1=8'b0;
if (b_in[2]) ashift2=a_in;
else ashift2=8'b0;
if (b_in[3]) ashift3=a_in;
else ashift3=8'b0;
if (b_in[4]) ashift4=a_in;
else ashift4=8'b0;
if (b_in[5]) ashift5=a_in;
else ashift5=8'b0;
if (b_in[6]) ashift6=a_in;
else ashift6=8'b0;
if (b_in[7]) ashift7=a_in;
else ashift7=8'b0;
end

assign add1_in1 = {8'b00000000, ashift0};
assign add1_in2 = {7'b0000000, ashift1, 1'b0};
assign add2_in1 = add1_out;
assign add2_in2 = {6'b000000, ashift2, 2'b00};
assign add3_in1 = add2_out;
assign add3_in2 = {5'b00000, ashift3, 3'b000};
assign add4_in1 = add3_out;
assign add4_in2 = {4'b0000, ashift4, 4'b0000};
assign add5_in1 = add4_out;
assign add5_in2 = {3'b000, ashift5, 5'b00000};
assign add6_in1 = add5_out;
assign add6_in2 = {2'b00, ashift6, 6'b000000};
assign add7_in1 = add6_out;
assign add7_in2 = {1'b0, ashift7, 7'b0000000};
assign add8_in1 = add7_out;
assign add8_in2 = mac;
assign mac_out = add8_out;

adder16 add1 (add1_in1, add1_in2, add1_out),
 	add2 (add2_in1, add2_in2, add2_out),
 	add3 (add3_in1, add3_in2, add3_out),
 	add4 (add4_in1, add4_in2, add4_out),
 	add5 (add5_in1, add5_in2, add5_out),
 	add6 (add6_in1, add6_in2, add6_out),
 	add7 (add7_in1, add7_in2, add7_out),
 	add8 (add8_in1, add8_in2, add8_out);

always @ (negedge clk or posedge rst)
	if (rst) begin
		mac = 8'b00000000;
		end
	else begin
		mac = mac_out;
		end

always @ (posedge clk or posedge rst)
	if (rst) begin
		a_in = 4'b0000;
		b_in = 4'b0000;
		end
	else begin
		a_in = a;
		b_in = b;
		end
endmodule


module adder16 (a, b, out);
input [15:0] a;
input [15:0] b;
output [15:0] out;

wire c1, c2;

adder8
	a0 (a[7:0], b[7:0], 1'b0, out[7:0], c1),
	a1 (a[15:8], b[15:8], c1, out[15:8], c2);

endmodule


module adder8 (a, b, ci, out, co) ;

input [7:0] a;
input [7:0] b;
input ci;
output [7:0] out;
output co;

wire c1, c2, c3, c4, c5, c6, c7;

full_adder
	a0 (.a(a[0]), .b(b[0]), .cin(ci), .out(out[0]), .cout(c1)),
        a1 (.a(a[1]), .b(b[1]), .cin(c1), .out(out[1]), .cout(c2)),
        a2 (.a(a[2]), .b(b[2]), .cin(c2), .out(out[2]), .cout(c3)),
        a3 (.a(a[3]), .b(b[3]), .cin(c3), .out(out[3]), .cout(c4)),
        a4 (.a(a[4]), .b(b[4]), .cin(c4), .out(out[4]), .cout(c5)),
        a5 (.a(a[5]), .b(b[5]), .cin(c5), .out(out[5]), .cout(c6)),
        a6 (.a(a[6]), .b(b[6]), .cin(c6), .out(out[6]), .cout(c7)),
        a7 (.a(a[7]), .b(b[7]), .cin(c7), .out(out[7]), .cout(co));
        
endmodule


module full_adder (a, b, cin, out, cout) ;

input a, b, cin;
output out, cout;

wire w1, w2, w3;

XOR3 x1(.O(out), .I0(a), .I1(b), .I2(cin));
AND2 a1(.O(w1), .I0(a), .I1(b)),
     a2(.O(w2), .I0(a), .I1(cin)),
     a3(.O(w3), .I0(b), .I1(cin));
OR3 o1(.O(cout), .I0(w1), .I1(w2), .I2(w3));

endmodule


module test_fsm (clk, rst, agen, bgen, macgen, end_test);

input clk;
input rst;
output [7:0] agen;
output [7:0] bgen;
output [15:0] macgen;
output end_test;

reg [7:0] agen;
reg [7:0] bgen;
reg [15:0] macgen;
reg end_test;

parameter [3:0] //synopsys enum STATE_TYPE
    s0 = 4'b0000,
    s1 = 4'b0001,
    s2 = 4'b0010,
    s3 = 4'b0011,
    s4 = 4'b0100,
    s5 = 4'b0101,
    s6 = 4'b0110,
    s7 = 4'b0111,
    s8 = 4'b1000,
    s9 = 4'b1001,
    s10 = 4'b1010;

reg [3:0] /* synopsys enum STATE_TYPE */ cs;
reg [3:0] /* synopsys enum STATE_TYPE */ ns;

//synopsys state_vector cs

    always @ (negedge clk or posedge rst) 
    begin
	if (rst) cs = s0;
	else cs = ns;
    end

////////////////////////////////////////
// Fill in your test pattern below
////////////////////////////////////////

    always @ (cs)
    begin 
    	case (cs) //synopsys full_case
            s0: begin
            	agen = 8'h0;
            	bgen = 8'h0;
            	macgen = 16'h0;
		end_test = 0;
		ns = s1;
	    end 
            s1: begin
            	agen = 8'h0;
            	bgen = 8'h0;
            	macgen = 16'h0;
		end_test = 0;
		ns = s2;
	    end 
            s2: begin
            	agen = 8'h0;
            	bgen = 8'h0;
            	macgen = 16'h0;
		end_test = 0;
		ns = s3;
	    end 
            s3: begin
            	agen = 8'h0;
            	bgen = 8'h0;
            	macgen = 16'h0;
            	end_test = 0;
		ns = s4;
	    end 
            s4: begin
            	agen = 8'h0;
            	bgen = 8'h0;
            	macgen = 16'h0;
            	end_test = 0;
		ns = s5;
	    end 
            s5: begin
            	agen = 8'h0;
            	bgen = 8'h0;
            	macgen = 16'h0;
            	end_test = 0;
		ns = s6;
	    end 
            s6: begin
            	agen = 8'h0;
            	bgen = 8'h0;
            	macgen = 16'h0;
            	end_test = 0;
		ns = s7;
	    end 
            s7: begin
            	agen = 8'h0;
            	bgen = 8'h0;
            	macgen = 16'h0;
		end_test = 0;
		ns = s8;
	    end 
            s8: begin
            	agen = 8'h0;
            	bgen = 8'h0;
            	macgen = 16'h0;
		end_test = 0;
		ns = s9;
	    end 
            s9: begin
            	agen = 8'h0;
            	bgen = 8'h0;
            	macgen = 16'h0;
		end_test = 0;
		ns = s10;
	    end 
            s10: begin
            	agen = 8'h0;
            	bgen = 8'h0;
            	macgen = 16'h0;
		end_test = 1;
		ns = s10;
	    end 
	endcase
    end 

endmodule