module lock_top (clk_pin, rst_pin, enter_pin, in_pin, out_pin, state_pin);

input clk_pin;
input rst_pin;
input enter_pin;
input [7:6] in_pin;
output[7:0] out_pin;

output[6:0] state_pin;
reg[6:0] state_pin;


wire clk, rst, enter;
wire [1:0] combo;
wire [7:0] out;
wire out_a;
wire out_b;
wire [2:0] states;

assign rst = ~rst_pin;


wire vdd;
wire out_1;
wire out_2;
wire out_3;
wire gnd;
assign vdd = 1'b1;
assign gnd = 1'b0;
PULLUP U2(.O(enter_pin));

// debounce your enter_pin here.  //////



////////////////////////////////////////

assign out[0] = out_a;
assign out[1] = out_b;
assign out[2] = vdd;
assign out[3] = vdd;
assign out[4] = vdd;
assign out[5] = vdd;
assign out[6] = vdd;
assign out[7] = vdd;

always @ (states) begin
	if (states == 3'b000) begin
		state_pin = 7'b1000000;			
	end else if (states == 3'b001) begin
		state_pin = 7'b1110011;
	end else if (states == 3'b010) begin
		state_pin = 7'b0100100;
	end else if (states == 3'b011) begin
		state_pin = 7'b0001100;
	end else if (states == 3'b100) begin
		state_pin = 7'b0010011;
	end else if (states == 3'b101) begin
		state_pin = 7'b0001001;
	end else if (states == 3'b110) begin
		state_pin = 7'b0001000;
	end else if (states == 3'b111) begin
		state_pin = 7'b1100011;
	end else begin
		state_pin = 7'b0000000;
	end
end


assign out_pin = ~out;
assign combo = in_pin[7:6]; 


assign clk = clk_pin;

lock alock (.reset(rst), 
	    .enter(enter), 
	    .combo_in(combo), 
	    .clk(clk), 
	    .openlock(out_a), 
	    .error(out_b),
	    .st(states));
endmodule