Fall 1996,
Spring 1997,
Fall 1997,
Spring 1998,
Fall 1998,
Spring 1999,
Fall 1999,
Spring 2000,
Fall 2000.

**Final Exam, Friday, 11 May, 12:30-3:30, 237 Hearst Gym!****Final Project Report Specification (word97, pdf)****Final Project Extra Credit Point Specification (word97, pdf)**

- Catalog Description
- Course Information (Goals, Syllabus, Times and Locations, Textbook, Grading)
- Course Staff (Instructor, Teaching Assistants, Readers)
- Course Calendar
- Homework Policy, Lab Policy, Public Discussion
- Technical Discussion

*CS 150. Components and Design Techniques for Digital Systems*.
(5) Three hours of lecture, one hour of discussion, and three hours of laboratory
per week. Prerequisites: 61C, Electrical Engineering 40 or 42. Basic building
blocks and design methods to contruct synchronous digital systems. Alternative
representations for digital systems. Bipolar TTL vs. MOS implementation
technologies. Standard logic (SSI, MSI) vs. programmable logic (PLD, PGA).
Finite state machine design. Digital computer building blocks as case studies.
Introduction to computer-aided design software. Formal hardware laboratories
and substantial design project. Informal software laboratory periodically
throughout semester. (F,SP) Katz, Newton, Pister.

- Understand digital logic at the gate and switch level including both combinational and sequential logic elements.
- Understand clocking methodologies to manage information flow and preservation of circuit state.
- Appreciate digital logic specification methods and the compilation process that transforms these into logic networks.
- Gaim experience with computer-aided design tools for implementation with programmable logic devices.
- Appreciate the advantages/disadvantages between hardware and software implementations of a function.

- Introduction to modern digital logic design
- Combinational logic
- Switch logic and basic gates
- Boolean algebra
- Two-level logic
- Regular logic structures
- Multi-level networks and transformations
- Programmable logic devices
- Time response
- Case studies

- Sequential logic
- Networks with feedback
- Basic latches and flip-flops
- Timing methodologies
- Registers and counters
- Programmable logic devices
- Case studies

- Finite state machine design
- Concepts of FSMs
- Basic design approach
- Specification methods
- State minimization
- State encoding
- FSM partitioning
- Implementation of FSMs
- Programmable logic devices
- Case studies

- Elements of computers
- Arithmetic circuits
- Arithmetic and logic units
- Register and bus structures
- Controllers/Sequencers
- Microprogramming

- Computer-aided design tools for logic design
- Schematic entry
- State diagram entry
- Hardware description language entry
- Compilation to logic networks
- Simulation
- Mapping to programmable logic devices

- Practical topics
- Non-gate logic
- Asynchronous inputs and metastability
- Memories: RAM and ROM
- Implementation technologies

Lecture: T, Th 2:00-3:30, 10 Evans

Discussions: M 1:00-2:00 (6 Evans), M 2:00-3:00 CANCELLED, M 3:00-4:00 CANCELLED,
W 1:00-2:00 (4 Evans), NEW ROOM! W 2:00-3:00 (3105 Etcheverry), NEW Th 1:00-2:00
(241 Cory); You may attend any discussion section.

Laboratory Lecture: F 2:00-3:00, 10 Evans

Laboratories: M, W, Th 9:00-12:00; M, T, W, Th 5:00-8:00; Make-up F 10:00-12:00
(all in 204B Cory Hall)

Lab/Discussion Section Assignments

R. H. Katz, *Contemporary Logic Design*, Addison Wesley Publishing
Company, Reading, MA, 1993.

New evolving draft of a second edition (rough and incomplete)

- Homeworks: 10%
- Laboratories: 20%
- Midterms (2): 20%
- Final Project: 30%
- Final Exam: 20%

Professor Randy
H. Katz, Computer Science Division, EECS Department, 637 Soda Hall,
510-642-8778.

Office Hours: Th 12:00-2:00 PM and by appointment. E-mail: randy@cs.Berkeley.edu

**Head TA**: PoYan (neewok@uclink4.berkeley.edu); Office Hours: Tu 1-2 PM, 204B Cory- Steve Fang (stfang@cory.eecs.berkeley.edu); Office Hours: W 1-2 PM, 204B Cory
- Mark Feng (wushufeng@hotmail.com); Office Hours: W 4-5 PM, 204B Cory
- Neha Kumar (neha@cory.eecs.berkeley.edu); Office Hours: W 3-4 PM, 204B Cory
- Mike Lowey (MLowey150@hotmail.com); Office Hours: Tu 2-3 PM, 204B Cory
- Sammy Sy (sammysy@uclink4.berkeley.edu); Office Hours: M 4-5 PM, 204B Cory
- Laura Todd (laranth@cory.eecs.berkeley.edu); Office Hours: Tu 11-12 PM, 204B Cory
- Howard Tsai (htsai@uclink4.berkeley.edu); Office Hours: Th 4-5 PM, 204B Cory
- Jeff Tsai (jmtsai@cory.eecs.Berkeley.edu); Office Hours: M 3:00-4:00 PM, 204B Cory

- John Choy (mchoy@cory.eecs.Berkeley.edu)
- Wen Hui Guan (guanwh@yahoo.com)
- Binh Ho (binhh@cory.eecs.Berkeley.edu)

- Assignments are distributed on Thursdays, collected the following Friday at noon
- Submit assignments to CS150 homework box, on door of Cory 218
- Homework is graded on effort, not correctness
- See calendar on this web page for handouts

- Please attend a discussion section to hear about the solutions to the exam. This will usually take place during the week following the return of the exam.
- Regrades are by written petition only. The petition should succinctly state why you believe that your solution is correct when we believed it to be wrong. These should be given to the instructor.

- Post/receive announcements, questions, and discussion
- UseNet news group: ucb.class.cs150
- student e-mail list: eecs150@cory.eecs.berkeley.edu (please use judiciously!)

- Xilinx Foundation 2.1 online manuals -- (fast, searchable web interface to all Xilinx docs)
- Xilinx Library Guide -- (PDF 9MB)
- Xilinx XC4000E / XC4000X -- data sheet (PDF 727KB)
- STMicroelectronics M27C4001 EPROM -- data sheet (PDF), wrap-ID (TeX, PDF)
- Motorola MOC5009 Optoisolator -- data sheet (PDF), wrap-ID (TeX, PDF)
- Analog Devices AD1866 DAC -- data sheet (PDF), wrap-ID (TeX, PDF)
- National Semiconductor LM4862 "Boomer" audio amplifier -- data sheet (PDF), wrap-ID (TeX, PDF)

Page maintained by: Randy H. Katz

Last updated: 3 May 2001