General Guide to Debugging

1. Read the logfile output from the Xilinx Design Manager to check for suspicious warnings (see below: Reading the Logfile).
2. Check wiring of components for proper connections.  (Important note:  Chips should never be hot.)
3. Bad signals should be traced back to its origin.  This can be done in Xilinx by setting up debugging outputs.  Send signals to unused output pins (using OPAD's) or LED's to watch the internal values.
4. Check the test equipment before starting to debug.  There's nothing worse than spending an hour debugging your circuit with the logic analyzer to find that the pod is broken.
5. Since debugging is a process of elimination, tests that eliminate large portions of a circuit from considerations are the most useful.
6. Find out what is wrong specifically and think about what might cause the incorrect output that you see.

Reading the Logfile for Errors

Here's an example of some error messages:

WARNING:basnu - logical net "$1I48/$1I1/CLK" has no driver
WARNING:basnu - logical net "$1I6/$1I1/CEO" has no load

All components have names assigned to them by default.  These names identify a component or net all the way down to the lowest level.

In the first example above, "$1I48/$1I1/CLK" is an input pin called CLK which does not have a signal coming in.  No driver errors are usually bad because components in a design need to have all their inputs specified.  The question now is which component is it that doesn't have a clock input?  Instead of looking through all your pages of schematic, you can look at the name of the component.

From your top-level schematic, look for the component with the name $1I48.  The name of a selected component is displayed on the bottom left hand corner of the Viewdraw schematic window.  We know that it's on the first page because the name starts with a '1'.  Once you're looking at the correct page of your schematic, you can choose Edit->Select from the menu and search for the name $1I48.  (Make sure that you use the object type name for things with $'s in them.  If it's a label, that you're searching for, set the object type to label.)

Once you've found the correct component, you'll have to push into the component's schematic.  Now look for the component with the name $1I1.  When you've found it, check to make sure that there is a signal driving the CLK pin.

The deeper a component is in the design, the longer it's name will be.

The warning message, "$1I6/$1I1/CEO," says that there is an ouput pin called CEO which is not attached to anything.  This is okay because it's completely valid to ignore outputs.  However, check to make sure that you really do want to ignore that particular output.  In this example, the warning comes from a counter where the carry enable out signal has been ignored.

Instead of stopping the compilations on these warnings, Xilinx will trim away unused/unsourced components figuring that they're not important.  It's possible that your entire designed might be considered unneccessary and be trimmed away if you mislabel your clock net!
 

Known Software Peculiarities, and Other Errors

• EDIF generates warnings about schematics being newer than WIR files

Lots of software problems are caused by failing to update your WIR files before compiling/simulating.  To update WIR files manually, open a command prompt, go to your project directory, and run

check -p top-level-schematic-name
 

• VSM Error:  Can't find pulldown.1

Everybody probably knows about this by now, but you can't run VSM on a design with a readback circuit in it.  Delete it from your schematic before running VSM.  Put it back before compiling to a .bit file.
 

• LM/Flex Error

The license server is acting up.  If it's just on your computer, wait, then try again.  If this happens to everybody's computer at once, the server's crashed.  E-mail cs150support@deepthought.eecs.berkeley.edu  (there's no need for everybody to send a message.... one message will do).  The current problem with the license server when lots of people are logged on is being looked at.
 

• Libraries/proj directories don't appear when I choose File->Open in Viewdraw

Make sure your project manager is open and you've set you libraries and working directory correctly.  Also make sure that you save your project files after making any changes and before your open the first copy of Viewdraw.
 

• XDM error - Net has multiple drivers

Two possibilities.  You either have two different outputs tied together (for example, if the output from two gates are connected to the same net), or you've created a symbol for you top-level schematic.  Your top-level schematic should not have a symbol.
 

• VSM or EDIF warning:  WIR and SCH are from two different directories

Two different schematics should never have the same filename.  If, for example, both you and your partner are working on different versions of a schematic and both of your project directories are in the searchpath specified in Project Manager, EDIF or VSM might compile using your partner's WIR files instead of yours.  This happened in lab7.  If you called your own schematic lab7.1 you might or might not have had conflicts with the TA-provided lab7.1.
 

• HW Debugger Error:  INIT does not go high

A few things to check:

1. Are all your chips wired correctly?  They should not be hot.
2. The bottom bank of DIP switches should all be open except for 7 (which enables the reset button).  These switches control some of the configuration options on the Xilinx chip.
3. Did you compile for the correct Xilinx chip?  In XDM make sure the settings are: XC4005-PC84-4.
 
 

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