Footnotes
- ...
- Unfortunately, there is a problem with some
software under NT 4
- ...
- Nets with the
same name in different components are not connected.
- ...
- Unfortunatly, the Xilinx libraries do not have reliable
timing information for real designs, so these delays should not be
used when designing for the Xilinx. It is actually impossible to
accurately model the gate delays in an FPGA, as we will discuss
later.
nweaver@cs.berkeley.edu