Week | Date | Lecture & Readings | Homework & Worksheets | Lab & Project |
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1 | Th 8/23 | Lec #1: Course Introduction |
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2 | Tu 8/28 | Lec #2: Digital Abstraction; Lab0, Structural Verilog; Transistors and gates |
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Th 8/30 | Lec #3: FSMs; Lab1, Behavioral Verilog; Canonical Forms |
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3 | Tu 9/4 | Lec #4: FSMs in Verilog; transistors to flip flops |
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Th 9/6 | Lec #5: Lab2: testbenches, MIPS ALU; configurable logic |
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4 | Tu 9/11 | Lec #6: SAR ADC controller; FPGA circuits |
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Th 9/13 | Lec #7: PALs,PLAs; Memory; K-maps |
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5 | Tu 9/18 | Lec #8: RAM, counters, LFSR |
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Th 9/20 | Lec #9: UART, K-maps |
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6 | Tu 9/25 | Lec #10: MIPS |
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Th 9/27 |
Lec #11: Pipelined MIPS |
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7 | Tu 10/2 |
Lec #12: 5-stage, 3-stage |
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Th 10/4 | Lec #13: 3-stage; Memory Mapped IO |
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8 | Tu 10/9 | Lec #14: Stack, procedures, interrupts & exceptions |
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Th 10/11 | Lec #15: Interrupts, MIPS COP0, ISRs |
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9 | Tu 10/16 | Lec #16: Midterm review; Caches |
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Th 10/18 | Lec #17: Midterm in class. Open book, open notes. |
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10 | Tu 10/23 | Lec #18: Interrupt implementation, ISRs |
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Th 10/25 | Lec #19: FIFOs, OS support, ALU |
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11 | Tu 10/30 | Lec #20: Adders, Shifters, Multipliers |
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Th 11/1 | Lec #21: Project, Video signals |
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12 | Tu 11/6 | Lec #22: DRAM |
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Th 11/8 | Lec #23: SDRAM |
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13 | Tu 11/13 | Lec #24: SDRAM, DMA |
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Th 11/15 | Lec #25: IC cost model, pixel addressing, SDRAM timing |
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14 | Tu 11/20 | Lec #26: GPUs |
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Th 11/22 | Thanksgiving! |
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15 | Tu 11/27 | Lec #27: |
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Th 11/29 | Lec #28: |
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16 | RRR week |
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17 | Fri 12/14 | Final Exam, 7-10pm |
Final Review Questions *Updated* Final Review Presentation Chip Cost (txt) Chip Cost (xlsx) |