HW 8

1. Scan the datasheet for the DVI driver (Chrontel CH7301) on the ML505 board (and be grateful that we're not asking you to write the interface to it).
   1. In table 2, which format has the highest pixel rate?
   2. From section 3.3, and Figure 4, describe how the two 12 bit data values P0a and P0b turn into three 8 bit RGB pixel values.
2. In the lecture notes from lecture 13 last semester,
   1. how many ports are there on the SRAM cell on page 13? Are the read, write, or read/write ports?
   2. On slide 23, how many bits of distributed RAM, and block RAM is available?
   3. The block RAM timing is shown on page 25. Redraw the figure with the WE line inverted.
3. On the timing diagram for your IS61 SRAM, draw the control signals and the contents of the address and data lines under the conditions below. Be careful with clock edges, setup and hold times, and the state of the data lines (driven, high-Z). Note that unlike block RAM on the FPGA, there is no separate "Data In" and "Data Out" for this chip - that's just a convenient way to show the signals. Assume that "Data Out" is what the RAM is driving onto the data lines, and "Data In" is the signal coming from the FPGA.
   1. In every odd cycle, the video driver is reading pixel data from the RAM (to send to the DVI chip). The reads are consecutive, starting at address 0x100. The data in memory at those locations starts at 0xF0 and decreases by 1 at each subsequent address.
   2. In every even cycle, your pixel drawing engine is writing the pixels in a diagonal line. The first pixel address is 0x2000 and pixel addresses in the line are separated by 0x501. The pixel value (data) being written starts at 0 and increases by 1 each pixel.