HW 7

1. DDCA Chapter 8, problem 24
2. Implement the three-ported register file from DDCA Figure 5.43/47 with N=5 and M=32. This is a synchronous memory, so use flip flops as storage elements.
   1. Use hierarchical design, from a block diagram down to individual gates.
   2. Estimate the number of gates in your design
   3. Estimate the area of your design in a 90nm process with 200k gates/mm2
   4. Estimate the cost of your design if tested silicon costs $0.10/mm2 in this process. What does this say about the cost/benefit of adding multiple shadow register files to the MIPS architecture?
3. There is a sycnhronous SRAM chip on the ML505 board, the IS61Nxx25636. Read the datasheet (it's on the docs page of the class website).
   1. In the terminology of DDCA Figure 5.43, what are N and M for this chip?
   2. Looking at the block diagram for the chip, what is different about the data I/O lines relative to Figure 5.43?
   3. On page 18, what is the delay from the presentation of an address during read until the data is ready?
   4. On page 20, for the data I/O lines on each rising edge of the clock, circle the important control inputs that affect the I/O lines in that cycle.