HW 6

1. DDCA Chapter 7, problems 12, 35
2. Write an interrupt handler in assembly to handle the RTC interrupt. When an RTC interrupt occurs, the ISR needs to increment a memory location. Let's assume that it's at memory location 0x10007010 (like the array in example code 6.21). Assume that you have to save any register that you touch.
3. For the code in example 6.27, Harris & Harris already showed us what the stack looks like at different stages when calculating 3 factorial (figure 6.26). Your job is to draw that stack under these different assumptions:
   1. your RTC interrupt is raised while the processor is executing the instruction at location 0xA0 (the second time, i.e. for n=2)
   2. your RTC interrupt is raised while the processor is executing the instruction at location 0x94 (the second time)
   3. your RTC interrupt is raised while the processor is executing the instruction at location 0x90 (the second time)
4. Write an interrupt handler in assembly to handle the UART0 RX interrupt. Assume that the UART is set up as in Lab5, but with the addition of an interrupt. On an RX interrupt the handler should put the received byte at the end of a circular FIFO. Assume that the FIFO starts at 0x10007010, has a maximum length specified in 0x10007000C, and start and end pointers at 0x10007004 and 0x10007008 respectively.
   1. How many cycles does it take your ISR to execute?
   2. If you had a 4 byte FIFO in the UART itself (like the PIC32), and the interrupt happened when the FIFO was full, how would that affect the execution time of your ISR?