Computer Science 150:
Components and Design Techniques for Digital Systems
TAs Austin Doupnik,
Michael Eastham,
Suhas Gaddam
Fall 2010 - Home
Home |
Schedule |
Documents |
Assignments |
Labs |
Staff |
Syllabus |
Links |
Old Websites
Lectures: Tuesday and Thursday, 2:00-3:30PM, 306 Soda
Lab Lecture: Friday, 2:00-3:00pm, 125 Cory
Important Announcements
Check Frequently
- The TAs will hold a review session from 1-3 PM on Friday, December 10th. Please email us questions from past homeworks or exams you would like to see covered.
- Grades for the project design reviews and checkpoints have been posted to bSpace. Please check them for discrepencies.
- There has been a small update to the bootloader. Make sure the archive you download has a VERSION file with the contents REV2
- The bootlader has been posted to the Lab page under Checkpoint 3 Lab Files.
- Some minors errors in the checkpoint 3 document have been corrected.
- The checkpoint 3 document and lecture slides have been posted. Be ready to do design reviews next week.
- TA solution to CP1 posted, please report bugs.
- Discussion 9AM Friday Nov. 12th is cancelled
- Reminder: Checkpoint 2 design documents due in lab this Tuesday and Wednesday, November 2nd and 3rd
- SVN repositories are ready, if you want one, please email Austin with the list of logins that should have access
- Checkpoint 1 may be turned in as late as Friday, October 29
- All previous APMIPS updates have been towards fixing a single bug. It is a huge pain,
so once again the APMIPS files have been updated, but only the InstructionMemory module has ever been
touched. Furthermore, there is a new guide to read
- Reminder: Checkpoint 1 design documents due in lab this Tuesday and Wednesday, October 19th and 20th
- All of Lab 5 is working now. Chipscope has been upgrade on all computers except 125-{17,42,39,43,44}
- Lab 5 is *BROKEN* the version of chipscope installed on the lab machines does not match the version of the cores generated
by coregen, we apologize. As as a temporary fix try generating the cores on iserver1.eecs or isererver2.eecs. These have an older
version of coregen on them, and *MAY* work.
- No lab lecture Friday September 30th.
- Solutions for homework 4 posted
- Some guidelines for writing design documents for Lab 5 have been posted on the Documents page under Tutorials
- Lab 5 posted
- Solutions for Homework 1 and 2 posted
- Revision H of the Lab 3 lab document has been posted. It fixes some minor typos
- The Schedule has been updated to reflect new times for Mike's section and office hours
- Lab 3 posted
- Lab 2 posted
- If you still need card key access, please see Alice in 390 Soda
- Problem set 1 posted
- Readings have been updated under Assignments
- TA office hours have been updated under Staff
UC Berkeley EECS150 would like to thank Xilinx for their continued support.
The FPGA toolflow, as well as the XUPv5 Virtex-5 LX110T platform are made available through a generous donation by Xilinx.
Copyright UC Berkeley EECS150 http://inst.eecs.berkeley.edu/~cs150