10-09-2007

IMPORTANT ANNOUNCEMENTS REGARDING LAB 5 AND THE PROJECT
Please read the entire post!

Topics of this post include:

• Lab 5 (Chipscope)
• Project
  • Design Reviews
  • Checkoff Procedures and Code Submission
  • Late Policy and Slip Days
  • Partial Credit / Black Boxes

• We've noticed that many groups are retroactively putting Chipscope into their designs after getting audio output working. These groups have missed the entire point of this lab, which is to learn how to use Chipscope to debug hardware.
• Perhaps we didn't emphasize this enough, but Chipscope will be absolutely essential in helping you debug your project. The sooner you start learning the ins and outs of Chipscope, the better off you'll be when working on the project.
• Note that in Lab 5, you will be required to demonstrate your knowledge of Chipscope in reading the signals coming in and out of the FIFO (as indicated on p.5, section 4.1 of the lab document).

• Prepare a thorough design document for each project checkpoint.
• Worth 10% of your checkpoint grade.
• Due within the first 10 minutes of your lab section.
• Both partners must be prepared to discuss and defend the design
• we will be asking both partners questions!
• **IMPORTANT** Please make a copy of your design document before your design review! We will be keeping a copy for grading purposes. You don't want to be stuck without a design document.
• We suggest using Microsoft Visio to make the block diagrams and FSMs. This is beneficial for several reasons:
  • You'll have your own copy after we collect your document for the review
  • Diagrams are easier to read
  • You can reuse the diagrams for the final report.
• Although we did not explicitly require timing diagrams for the first design document, we highly recommend making some timing diagrams for the first checkpoint, especially for the tricky SDATA_IN signal Udam mentioned.
  • You might find this stencil useful for making timing diagrams in Visio:
  • http://www.mvps.org/visio/FTP/TIMEDIA.VSS
• Recall, your design document should be thorough enough so that any other group can implement the entire checkpoint based solely on your document.

• For each project checkpoint, you will be required to submit the bit file for the checkpoint and all relevant Verilog and black box modules.
• Email your submissions to cs150fa07@gmail.com
• Submissions are due within the first 10 minutes of your lab section (see section below for policy on late submissions and slip days)
• During your checkoff, we may ask you to synthesize your design on the fly and/or ask you questions about the checkpoint.

• We are granting each group a total of four (4) slip days to distribute among the entire project.
• Slip days are rounded up (e.g., if you are in a 5-8PM lab, and we receive a submission at 5:21PM, it counts as an entire slip day) You may submit as many times as you like within a slip day.
• SLIP DAYS ARE NOT APPLICABLE ON WEEKENDS
  • The latest we will accept a project checkpoint using a slip day is Friday 5:09:59PM.
  • This is to prevent you from falling behind on later checkpoints (see section below for partial credit black box policy).
  • We realize that students in the Thursday evening section will only be able to use at most one slip day per checkpoint, but they have the advantage of having the most days after lab lecture to work on the checkpoint.
• Stay tuned for policy on late submissions after all 4 slip days have been used.

• For each project checkpoint (except perhaps the last), you will have the choice of accepting a 0 on the checkpoint in exchange for a black box implementation of the checkpoint.
  • However, you may redeem up to 50% of the points if you can fully fix your checkpoint within two weeks after the checkpoint is due.
  • The black box will allow you to move on for the later parts of the project.