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EECS 150 Components and Design Techniques for Digital Systems
λ beef
EECS 150 Fall 2005
MW 1:00-2:30PM
306 Soda Hall
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Project Grading Breakdown
Checkpoint 1: 10%
Checkpoint 2: 10%
Checkpoint 3: 30%
Checkpoint 4 / Final Checkoff: 30%
Report: 20%
Extra Credit: Up to 20%
Project information & due dates
Project writeup description
Design review instructions
Checkpoint 1 [
zip
,
demo bitfile
,
lab lecture
,
Solution
]
Checkpoint 2 [
zip
,
demo bitfile
,
lab lecture
,
Solution
]
Checkpoint 3 [
zip
,
lab lecture 1
,
lab lecture 2
]
Checkpoint 4 / Final Project [
pdf
,
project demo bitfile
,
lab lecture
]
No Verilog is provided for this checkpoint (no zip file).
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UC Berkeley
http://www-inst.eecs.berkeley.edu/~cs150/
EECS 150 Fall 2005