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Wk |
Date |
Lecture / Reading |
Homework / Quiz |
Lab / Project |
| 1 | M 8/29 | Lecture #1: Course Administration [ppt, pdf] Quick Review: The Many Representations of Hardware | Background Questionaire and Diagnostic Quiz [doc, pdf]
Quiz #0 Solution [jpg]
HW #1 (Revised) [doc, pdf] Solution: [doc] |
|
| W 8/31 | Lecture #2: Combinational Logic [ppt, pdf]
Readings: K&B, Ch.1: 1.1-1.4, pp. 1-27; Ch.2: 2.1-2.4, pp. 33-65; |
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| 2 | M 9/5 | Labor Day | HW #2 (Revised!) [doc, pdf] Due 9/16 at 2:10PM Solutions: [doc, pdf] Quiz #1 Solution [jpg] |
Lab Lecture #2: Designing with Verilog
[ppt,
pdf,
webcast] HW #1 due Lab #1: CAD Tools [doc, pdf, zip] |
| W 9/7 | ||||
| 3 | M 9/12 | Lecture #4: Verilog Hardware Description Language [ppt, pdf(2 up), pdf(6 up)] | HW #3
[doc,
pdf] Due 9/23 at 2:10PM Solutions: [doc, pdf] Quiz #2 Solution [jpg] |
Lab Lecture #3: Lab #3[ppt,
pdf,
webcast] Lab #2: Designing with Verilog [doc, pdf, zip] Solutions: [zip] |
| W 9/14 | Lecture #5: Basic Finite State Machines Flip-Flops, Registers, Shifters, Counters [ppt, pdf(2 up), pdf(6 up)] Readings: K&B, Ch.3: 3.6: pp. 139-146; Ch.6: 6.1, 6.3, pp.259-278, 289-298; |
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| 4 | M 9/19 | Lecture #6: Moore vs. Mealy Machines
[ppt,
pdf(2 up),
pdf(6 up)] |
HW #4
[doc,
pdf] Due: 10/7 at 2:10PM Solutions: [doc, pdf] Quiz #3 Solution (Page 1 [jpg], Page 2[jpg]) |
Lab Lecture #4: Debugging
[ppt,
pdf] HW #3 due Lab #3: Implementation of FSMs [doc, pdf, zip] |
| W 9/21 | Lecture #7: Verilog for State Machines
[ppt,
pdf(2 up),
pdf(6 up)] Readings: K&B, Ch.7: 7.1-7.3, pp. 308-339. |
|||
| 5 | M 9/26 | Lecture #8: Midterm I Review |
Lab Lecture #5: Logic Analyzers [ppt,
pdf,
webcast]
Lab #4: Debuggings [doc, pdf, zip] |
|
| W 9/28 | Midterm I Solutions: [zip] |
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| 6 | M 10/3 | Lecture #10: FSM Synthesis, State
Machine Timing [ppt, pdf(2 up), pdf(6 up)] |
HW #5
[doc,
pdf] Due: 10/14 at 2:10PM Solutions: [doc, pdf] Quiz #4 [doc, pdf] Solution [jpg] |
Lab Lecture #6: Project Checkpoint #1
[pdf,
pdf,
webcast]
(one week) Lab #5: Logic Analyzers [doc, pdf, zip] |
| W 10/5 | Lecture #11: Case Study SDRAM/Memory Controller [ppt, pdf(2 up), pdf(6 up)] Readings: K&B, Ch.6: 6.2.1, 6.2.2, pp. 279-282; Ch.10: 10.4, pp. 467-482. |
|||
| 7 | M 10/10 | Lecture #12: Project Description (Electronic Etch-a-Sketch) [ppt, pdf(2 up), pdf(6 up)] |
HW #6 [doc,
pdf] Due: 10/21 at 2:10 PM Solutions: [doc, pdf] Quiz #5 solution [jpg] |
Lab Lecture #7: Project Checkpoint #2
[ppt,
pdf]
webcast] (one week) HW #5 due Checkpoint #1: Game Controller Interface [zip, pdf, doc] Demo Solution: [bit] |
| W 10/12 | Lecture #13: Datapath Building Blocks
and Interconnection Strategies Arithmetic Units, Register Files, Shifters, FIFOs, Memories Point-to-Point, Single Bus, Mixed [ppt, pdf(2 up), pdf(6 up)] Readings: K&B, Ch.5: 5.5-5.7, pp.234-249; Ch.6: 6.3. pp. 289-295. CLD Chapter 11 [html] |
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| 8 | M 10/17 | Lecture #14: Datapath Control State Machines for Control, Register Transfer [ppt, pdf(2 up), pdf(6 up)] |
HW #7 [doc,
pdf] Due: 10/28 at 2:10 PM Solutions: [doc, pdf] Quiz #6 solution [doc, pdf] |
Lab Lecture #8 Project Checkpoint #3
(two weeks) [ppt, pdf, webcast] HW #6 due Checkpoint #2: LCD Interface [doc, pdf, zip] Demo Solution: [bit] |
| W 10/19 | Lecture #15: Datapath Control Microprogrammed State Machines [ppt, pdf(2 up), pdf(6 up)] Readings: K&B, Ch.9: 9.1-9.4, pp. 401-446. CLD Chapter 12 [html] |
|||
| 9 | M 10/24 | Lecture #16: Control Timing and Retiming [ppt, pdf(2 up), pdf(6 up)] |
HW #8 [doc,
pdf] Due: 11/4 at 2:10 PM Solution: [doc, pdf] Quiz #7 solution [jpg] |
Lab Lecture #9: Checkpoint #3
(continued) [ppt, pdf, webcast] HW #7 due Checkpoint #3 Memory Interface (continued) [doc, pdf, zip] |
| W 10/26 | Lecture #17: Control Parallelism and
Pipelining (material integrated into Lecture #16) |
|||
| 10 | M 10/31 | Lecture #18: Testing, Fault Models,
Design for Test [ppt, pdf(2 up), pdf(6 up)] |
HW #9 [doc,
pdf] Due: 11/18 at 2:10 PM Solution: [doc, pdf] Quiz #8 [doc, pdf], Solution [jpg] |
Lab Lecture #10: Checkpoint 4 and Putting the
Project
Together (two weeks) [ppt, pdf, webcast] HW #8 due |
| W 11/2 | Lecture #19: State Machine Optimization State Encodings, State Assignments, and State Partitioning [ppt, pdf(2 up), pdf(6 up)] Readings: K&B, Ch.7: 7.4, pp. 339-346; Ch.8: 8.1-8.3, pp. 356-386. |
|||
| 11 | M 11/7 | Lecture #20: Midterm II Review |
Veterans Day No Lab Lecture Checkpoint #4: Paint Engine [doc, pdf] Project Demo Solution: [bit] |
|
| W 11/9 | Midterm II Solution Page 1 [jpg], 2 [jpg], 3 [jpg], 4 [jpg], 5 [jpg], 6 [jpg], 7 [jpg], 8 [jpg], 9 [jpg], 10 [jpg], 11 [jpg], 12 [jpg], 13 [jpg], all pages [zip] |
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| 12 | M 11/14 | Lecture #22: State Machines, Signaling,
Metastability, Arbiter Design, Hazards [ppt, pdf(2 up), pdf(6 up)] |
HW #10 [doc,
pdf] Due: 12/2 at 2:10 PM Quiz #9 Solution [jpg] |
HW #9 due |
| W 11/16 | Lecture #23: Arithmetic Circuits Basic Building Blocks [ppt, pdf(2 up), pdf(6 up)] Readings: K&B, Ch.3: 3.5, pp. 129-139; Ch.6: 6.2.3-6.2.5, pp.282-289. |
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| 13 | M 11/21 | Lecture #24: Arithmetic Circuits Combinational and Sequential Multiplier [ppt, pdf(2 up), pdf(6 up)] |
Thanksgivings No Lab Lecture |
|
| W 11/23 | Lecture #25: Design Methodology [ppt, pdf(2 up), pdf(6 up)] Readings: K&B, Ch.5: 5.8, pp. 249-253; Ch.10: 10.5, pp. 482-487. |
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| 14 | M 11/28 | Lecture #26: Logic Design with Switches [ppt, pdf(2 up), pdf(6 up)] |
Quiz #10 Solution [jpg] | No Lab Lecture |
| W 11/30 | Lecture #27: Evolution of FPGA Architecture [ppt, pdf(2 up), pdf(6 up)] | |||
| 15 | M 12/5 | Lecture #28: Power-Based Design Sorry no Power lecture this semester! |
No Lab Lecture PROJECT WRITE-UP DUE |
|
| W 12/7 | Lecture #29: Course Summary and Review [ppt, pdf(2 up), pdf(6 up)] |
| UC Berkeley | http://www-inst.eecs.berkeley.edu/~cs150/ | EECS 150 Fall 2005 |
