Midterm Exam I Outline ---------------------- Midterm I will cover lectures 1 through 8. Homework problems are typical of exam questions. Expect the exam questions to go into more depth than the quizzes and in some cases more depth than the homework questions. You should understand the basic concepts sufficiently well to apply them in new situations. On the exam, the concepts will be familiar to you but not necessarily the circuits and contexts. Lecture 1: Design constraints: performance (speed) cost (complexity) power (energy dissipation) Example systems optimized for each of these. The idea of a design tradeoffs between constraints. Examples of hierarchical representations of digital systems. Benefits of using hierarchy. Lecture 2: Basic characteristics of ICs and PC boards. Moore's Law. Rough classification of ICs. Qualitative operation of CMOS nFETs and pFETS. Structure of basic logic gates, tristate buffers, data latches, and edge-triggered flip-flops at the transistor. Operation of these circuits modeling transistors as switches. Basic operation of D-type flip-flops in the context of shifters and related circuits. Lecture 3: General model of digital systems comprising flip-flops and combinational logic. Determination of maximum clock frequency given characteristic delays of sub-components. The qualitative analysis of CMOS circuits as RC circuits. The origin of gate delay. Factors effecting gate delay, both inside a gate and at the logic circuit level. Qualitative wire delay modeling. Origin of delays associated with flip-flops. Lecture 4: Relationship among TTs, gate diagrams, and Boolean equations. How to convert from one to the other. Design of a ripple adder. Basic axioms of Boolean algebra. Application of theorems of Boolean algebra to algebraic simplification and proving equivalence. Relationship between DeMorgan's law and NAND and NOR gates. Lecture 5: Generating canonical forms from TTs. Applying K-maps to simplify SOPs and POSs expressions (including don't cares). Simple factoring to form multi-level logic circuits. Analysis of logic circuits for transistor count (and delay). Lecture 6: High-level structure of FPGAs. Why FPGAs and their relationship to other types of ICs. The structure of an ideal CLB and LUT. The LUT as a general function block. Mapping circuits to CLBs/LUTs. Lecture 7: Formal design process for Moore style FSMs: Translating from English language problem description to state transition diagram (STD). STD to state transition table (STT). STT to logic equations for next state and outputs. Circuit implementation with combinational logic and flip-flops. Motivation for one-hot encoding FSMs. One-hot encoded FSM circuit derivation directly from STT. Lecture 8: Definition of a netlist. Different forms A few basic concepts, and constructs of Verilog. Difference between structural and behavioral descriptions. Dataflow description of Boolean expressions.