////////////////////////////////////////////////////////////////////////// //EECS150 Fall 2002 //Common modules file //This file provides modules that are commonly used in designs //submit bugs in this file to normzhou@cs.berkeley.edu ////////////////////////////////////////////////////////////////////////// //NOTE: // many modules in this file are parameterizable. // The parameter in the begining of the module can be // overwriten with new values at instatiating time. //For example: // register #(16) myReg(.I(i), .O(o), .E(en), .C(clk), .R(rst)); // will overwrite the width parameter in the module with 16 // and create a 16 bit wide register. ////////////////////////////////////////////////////////////////////////// //variable width binary counter with enable and sync reset module counter (OUT, CLK, ENABLE, RESET); parameter width = 4; // to be overwriten output [width-1:0] OUT; input CLK; input ENABLE; input RESET; reg [width-1:0] OUT; initial OUT = 0; always @(posedge CLK) if (RESET) OUT <= 0; else if (ENABLE) OUT <= OUT + 1; endmodule // counter ////////////////////////////////////////////////////////////////////////// //variable width register with enable and sync reset module register (I, O, E, C, R); parameter width = 1; // to be overwriten input [width-1:0] I; output [width-1:0] O; input E; input C; input R; reg [width-1:0] O; initial O = 0; always @(posedge C) if (R) O <= 0; else if (E) O <= I; endmodule // register ////////////////////////////////////////////////////////////////////////// //variable width SET RESET flip-flop module SRflop (S, R, O, C); parameter width = 1; // to be overwriten input [width-1:0] S; input [width-1:0] R; output [width-1:0] O; input C; reg [width-1:0] O; initial O = 0; always @ (posedge C) if (R) O <= 0; else if (S) O <= 1; endmodule // SRflop ////////////////////////////////////////////////////////////////////////// //shift register module shiftReg(I, Data, Q, E, C, R); parameter width = 4; // to be overwriten input I, C, R, E; output Q; output [width-1:0] Data; reg [width-1:0] Data; initial Data = 0; always @ (posedge C) if (R) Data <= 0; else if (E) Data <= {Data[width-2:0], I}; assign Q = Data[width-1]; endmodule ////////////////////////////////////////////////////////////////////////// //loadable variable width circular shift by 4bit //register with synchronus reset module shiftLeft4_Ld (IN, OUT, CLK, LOAD, SHIFT, RESET); parameter width = 16; // to be overwriten input [width-1:0] IN; output [width-1:0] OUT; input CLK; input LOAD; input SHIFT; input RESET; reg [width - 1:0] OUT; initial OUT = 0; always @(posedge CLK) if (RESET) OUT <= 0; else if (LOAD) OUT <= IN; else if (SHIFT) OUT <= {OUT[width-5:0], OUT[width-1:width-4]}; endmodule // shiftBy4 ////////////////////////////////////////////////////////////////////////// //variable width shift by 4bit register with synchronus reset module shiftLeft4 (IN, OUT, CLK, SHIFT, RESET); parameter width = 4; // to be overwriten input [3:0] IN; output [width-1:0] OUT; input CLK; input SHIFT; input RESET; reg [width-1:0] OUT; initial OUT = 0; always @ (posedge CLK) if (RESET) OUT <= 0; else if (SHIFT) OUT <= {OUT[width-5:0], IN}; endmodule // shiftLeft4 ////////////////////////////////////////////////////////////////////////// //variable width rising edge catcher module upedge (I, O, C); parameter width = 1; // to be overwriten input [width-1:0] I; output [width-1:0] O; input C; reg [width-1:0] D0; reg [width-1:0] D1; always @(posedge C) begin D1 <= D0; D0 <= I; end assign O = ~D1 & D0; endmodule // upedge ////////////////////////////////////////////////////////////////////////// //variable width rising edge catcher module upedge_A (I, O, C); parameter width = 1; // to be overwriten input [width-1:0] I; output [width-1:0] O; input C; reg [width-1:0] D; always @(posedge C) begin D <= I; end assign O = ~D & I; endmodule // upedge ////////////////////////////////////////////////////////////////////////// //variable length debouncer (untested) // length = number of flip flops to use // debounce period = 2 ^ (length - 1) // (larger lenght)=(longer debounceing period) module bin_debounce (I, O, C); parameter length = 4; // to be overwriten input I; output O; input C; reg [length-1:0] cntr; initial cntr = 0; always @(posedge C) begin if (cntr[length-1] ^ I) begin cntr <= cntr + 1; end end upedge dbnc(.I(cntr[length-1]), .O(O), .C(C)); endmodule // bin_debounce ////////////////////////////////////////////////////////////////////////// //binary to segment LED converter (untested) // converts from 4bit input to coresponding module bin2HexLED (IN, SEGLED); input [3:0] IN; output [6:0] SEGLED; reg [6:0] SEGLED; always @(IN) begin case (IN) 4'h0: SEGLED <= 7'b0111111; 4'h1: SEGLED <= 7'b0000110; 4'h2: SEGLED <= 7'b1011011; 4'h3: SEGLED <= 7'b1001111; 4'h4: SEGLED <= 7'b1100110; 4'h5: SEGLED <= 7'b1101101; 4'h6: SEGLED <= 7'b1111101; 4'h7: SEGLED <= 7'b0000111; 4'h8: SEGLED <= 7'b1111111; 4'h9: SEGLED <= 7'b1100111; 4'hA: SEGLED <= 7'b1110111; 4'hB: SEGLED <= 7'b1111100; 4'hC: SEGLED <= 7'b1011000; 4'hD: SEGLED <= 7'b1011110; 4'hE: SEGLED <= 7'b1110011; 4'hF: SEGLED <= 7'b1110001; endcase end endmodule // HEXLED ////////////////////////////////////////////////////////////////////////// //binary to segment LED converter (untested) // converts from 6bit input to coresponding alphabetical display // on segment LED module CHARLED (SEGLED, IN); input [5:0] IN; output [6:0] SEGLED; reg [6:0] SEGLED; always @(IN) begin case (IN) 6'h00: SEGLED <= 7'b0111111; 6'h01: SEGLED <= 7'b0000110; 6'h02: SEGLED <= 7'b1011011; 6'h03: SEGLED <= 7'b1001111; 6'h04: SEGLED <= 7'b1100110; 6'h05: SEGLED <= 7'b1101101; 6'h06: SEGLED <= 7'b1111101; 6'h07: SEGLED <= 7'b0000111; 6'h08: SEGLED <= 7'b1111111; 6'h09: SEGLED <= 7'b1100111; 6'h0A: SEGLED <= 7'b1110111; 6'h0B: SEGLED <= 7'b1111100; 6'h0C: SEGLED <= 7'b1011000; 6'h0D: SEGLED <= 7'b1011110; 6'h0E: SEGLED <= 7'b1111001; 6'h0F: SEGLED <= 7'b1110001; 6'h10: SEGLED <= 7'b1101111;//G 6'h11: SEGLED <= 7'b1110100;//H 6'h12: SEGLED <= 7'b0110000;//I 6'h13: SEGLED <= 7'b0011110;//J 6'h14: SEGLED <= 7'b0001000;//K - not displayable "_" 6'h15: SEGLED <= 7'b0111000;//L 6'h16: SEGLED <= 7'b0001000;//M 6'h17: SEGLED <= 7'b1010100;//N 6'h18: SEGLED <= 7'b1011100;//O 6'h19: SEGLED <= 7'b1110011;//P 6'h1A: SEGLED <= 7'b0001000;//Q - not displayable "_" 6'h1B: SEGLED <= 7'b1010000;//R 6'h1C: SEGLED <= 7'b1101101;//S 6'h1D: SEGLED <= 7'b1111000;//T 6'h1E: SEGLED <= 7'b0011100;//U 6'h1F: SEGLED <= 7'b0001000;//V - not displayable "_" 6'h20: SEGLED <= 7'b0001000;//W - not displayable "_" 6'h21: SEGLED <= 7'b1110110;//X 6'h22: SEGLED <= 7'b1101110;//Y 6'h23: SEGLED <= 7'b0001000;//Z - not displayable "_" default: SEGLED <= 7'b0000000;// endcase end // always @ (IN) endmodule /////////////////////////////////////////////////////////// //NOTE: //The following modules are Xilinx Virtex FPGA primatives //for further infor mation about the functions of these //primatives please consult the xilinx online manuals at: //http://toolbox.xilinx.com/docsan/xilinx5/manuals.htm //under section Libraries Guide/Design Elements /////////////////////////////////////////////////////////// //BUFG is a xilinx primitive for global clock buffering module BUFG (I, O) /* synthesis syn_black_box */; input I; output O; //Behavior module of BUFG for simulation assign O = I; endmodule /////////////////////////////////////////////////////////// //16-Bit Shift Register Look-Up-Table (LUT) //with Carry and Clock Enable. module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D) /* synthesis syn_black_box */; parameter initData = 16'h0000; input D, CE, CLK; input A0, A1, A2, A3; output Q; //Behavior description of SRL16E for simulation reg [15:0] data; initial data = initData; always @ (posedge CLK) if (CE) data <= {data[14:0], D}; assign Q = data[{A3, A2, A1, A0}]; endmodule /////////////////////////////////////////////////////////// // Dualport block ram 512 x 8 // note this is untested verilog module RAMB4_S8_S8(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box output [7:0] DOA; output [7:0] DOB; input [8:0] ADDRA; input [7:0] DIA; input ENA; input CLKA; input WEA; input RSTA; input [8:0] ADDRB; input [7:0] DIB; input ENB; input CLKB; input WEB; input RSTB; //simulation code reg [511:0] data [7:0]; always @ (posedge CLKA) if (ENA) begin if (RSTA) DOA <= 0; else DOA <= data[ADDRA]; if (WEA) data[ADDRA] <= DIA; end always @ (posedge CLKB) if (ENB) begin if (RSTB) DOB <= 0; else DOB <= data[ADDRB]; if (WEB) data[ADDRB] <= DIA; end endmodule