| Name: _______________________________________ | Name: _______________________________________ |
| Lab Section: |
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What is ENTER connected to (include direct and indirect sources)? Why? |
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What do you expect to see to see when the lock is opened? |
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To where does the clock feed out? Why? |
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Why are CODE0 and CODE1 not debounced? |
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In terms of buttons, switch settings, and lights illuminating, give instructions for opening the lock. |
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Explain the three wire-wrap wires on the board. Why are they there? Why does SW 4-7 have to be closed? (Hint: look at a board and the demonstration board schematics) |
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By looking at the report files, how many CLBs does your design use? |
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1. Working Xilinx Lock |
TA: |
___________________ (50%) |
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2. Questions answered |
TA: |
___________________ (40%) |
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3. Turned in on time |
TA: |
___________________ (10%) |