| EECS150 Components and Design Techniques for Digital Systems | |
EECS150 Spring 2004 |
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Course Administration |
No Homework |
Lec #1: Instrumentation [PDF] [ |
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Transistor and Gate Logic [PDF]
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Combinational Logic [PDF]
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Lab #1: Instrumentation [ZIP] Lec #2: Cad Tool Flow [PDF] [ |
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Programmable Logic: PAL/PLA and FPGA [PDF]
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Verilog Hardware Description Language [PDF]
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Lab #2: Cad Tool Flow [ZIP] Lec #3: Verilog Simulation [PDF]
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Basic Finite State Machines: Flip-Flops,
Registers, Shifters, Counters [PDF] [ |
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Moore and Mealy Machines [PDF]
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Lab #3: Verilog Simulation [ZIP] Lec #4: Verilog Synthesis [PDF] [ |
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FSM Synthesis, State Machine Timing [PDF]
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Midterm I Review [PDF] [ |
No Homework |
Lab #4: Verilog Synthesis [ZIP] Lec #5: Debugging [PDF] [ |
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Midterm I (Info: [PDF], Solution: [ZIP], Grade Distribution: [PDF]) |
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24 Feb |
Case Study: SDRAM/Memory Controller [PDF]
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Lab #5: Debugging [ZIP] Lec #6: SDRAM Controller, I [PDF]
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26 Feb |
Project Description: Multimedia Network Router
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Datapath Building Blocks: Arithmetic Units,
Register Files, Shifters, FIFOs, Memories [PDF]
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Ckpt #1: SDRAM Controller (2 weeks) [ZIP] Lec #7: SDRAM Controller, II [PDF]
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Datapath Interconnection: Point-to-Point,
Single Bus, Mixed Strategy [PDF] [ |
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Datapath Control: State Machines for Control;
Register Transfer Abstraction [PDF] [ |
Ckpt #1: SDRAM Controller (Due) Lec #8: AC97 Control & Audio [PDF]
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Datapath Control: Microprogramming [PDF]
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Control Timing, Pipelining, Re-timing [ |
Ckpt #2: AC97 Controller (2 weeks) [ZIP] Lec #9: Tips and Techniques [PDF]
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Enjoy Yourselves |
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Midterm II Review [PDF]
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No Homework |
Ckpt #2: AC97 Audio (Due) Lec #10: Ethernet [PDF] [ |
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30 Mar |
Midterm II (Info: [PDF], Solution: [PDF], Grade Distribution: [PDF]) | |||
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Testing, Fault Models, Design for Test [PDF]
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State Machine Optimization, State Encodings,
and State Assignment [PDF] [ |
HW #8 [PDF] |
Ckpt #3: Ethernet [ZIP]
Lec #11: SDRAM & Routing [PDF]
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State Machines, Signalling, Metastability, Arbiter Design,
Hazards [PDF] [ |
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Arithmetic Circuits: Building Blocks [PDF]
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Ckpt #4: SDRAM & Routing (2 weeks) [ZIP] Lec #12: Routing & Design Integration [PDF]
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Arithmetic Circuits: Combinational and
Sequential Multiplier [PDF] [ |
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Evolution of FPGA Architectures [PDF]
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HW #10 [PDF] |
Ckpt #4: SDRAM & Routing (Due) Lec #13: Final Checkoff and The Report [PDF]
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No Lecture. |
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26 Apr | Project Early Checkoff Deadline (Files due @ 10am) |
No Homework |
Lab: Final Integration and Project Demonstration |
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Special Topics [PDF] [ |
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| 3 May | Project Final Checkoff Deadline (Files due @ 10am) |
Lab: Final Report [DOC] |
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| 7 May |
Project Report due @ 4pm in 125 Cory |
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12 May | Final Review (in the lab 125Cory @ 4-7pm) (Slides: [PDF], Whiteboard: [ZIP], Video: [ ]) |
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Final Exam, 12:30-3:30 in 10 Evans (BRING
2 BLUE BOOKS ) |
| Last Updated: 01/23/2005 by | [an error occurred while processing this directive] |
| Greg Gibeling |