UC Berkeley CS150
Agenda
Resources
Schedule
Staff
Syllabus
Project
Tutorials
Tools
Virtex-5 FPGA Documentation
XUPv5/ML505 Board Documentation
Protocols & Standards
Tutorials
Verilog always@ block
Verilog wire Vs. reg
Verilog Finite State Machine
ChipScope
ModelSim
Ready/Valid handshake
Tools
Visio Stencils
Dot Manual
for state diagrams.
Tikz-Timing Manual
for timing diagrams.
PS6 Source
with examples of using dot, tikz-timing, and LaTeX.
Virtex-5 FPGA Documentation
Family Overview
User Guide
Libraries Guide for HDL Designs
DC & Switching Characteristics
System Monitor
XtremeDSP Design Considerations
DSP: Designing for Optimal Results
Packaging & Pinout Specification
Xilinx Synthesis Technology
MicroBlaze Micro Controller
MicroBlaze Reference Manual
MicroBlaze Processor Local Bus v4.6
Xilinx FIFO Generator v9.1
Note AXI4 not available in Virtex5. Chap. 5 is most relevant for CS150.
Xilinx RAM based Shift Register Generator
XUPv5/ML505 Board Documentation
ML505/ML506/ML507 Evaluation Platform User Guide
ML505/ML506/ML507 Schematics
System ACE CompactFlash Solution
AD1981A Audio Codec
CH7301C DVI Transmitter Device
DVI Encoder Registers Read/Write Operation
AD9980 VGA Input CODEC
LCD High-level schematic
M25P32 Serial Flash Memory
ZBT synchronous SRAM (IS61NLP25636)
Numonyx StrataFlash Embedded Memory
Platform Flash In-System Programmable Configuration PROMS
Protocols & Standards
IEEE Verilog
AC97 Audio
I2C Bus
RS-232