`define half_cycletime 10000
`timescale 1 ps/1 ps

module lab4_testbench_skeleton;
   reg [15:0] IN;
   reg  R, CLK;
   wire [15:0] OUT;
   
   lab4_cir top(.IN(IN), .RST(R), .CLK(CLK), .OUT(OUT));

   always
     begin
	 #(`half_cycletime) CLK = ~CLK;
     end

   initial
     begin
     //Testbench code here
     end
   
endmodule