module lab3_cir (IN, E, R, CLK, OUT);
   input [7:0] IN;   
   input       E, R, CLK;
   output [7:0] OUT;

   reg [7:0] 	OUT;

   always @(posedge CLK) begin
      if (R)
	OUT <= 0;
      else if (E)
	OUT <= OUT + IN;      
   end

endmodule